Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

Abstract: The present invention relates to apparatuses, systems, and methods for defining positions where characters such as text, numbers, symbols, or the like are to be inscribed. Specifically, the positions may correspond with geometric shapes including, without limitation, arcs, circles, angles, lines, rectangles, or the like. Even more specifically, the apparatuses, systems, and methods define the positions using a plurality of points, such that information such as coordinates, angles, radiuses, perimeters, centers, heights, lengths, circumferences, or the like are not required. Further, measuring tools, prints, or operator skill/knowledge is not required.

Abstract: Described herein are molecules for use in organic light emitting diodes. Example molecules comprise at least one moiety A and at least one moiety D. Values and preferred values of the moieties A and D are described herein. The molecules comprise at least one atom selected from Si, Se, Ge, Sn, P, or As.

Abstract: A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.

Abstract: A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction.

Abstract: A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

Abstract: A substrate for an organic light emitting display device and an organic light emitting display device are provided. The substrate to the organic light emitting display device includes a protective layer having a non-flat shape; a first electrode on the protective layer and having the non-flat shape; and a bank layer on the protective layer and the first electrode. The bank layer having an opening for exposing the first electrode. The protective layer is formed at the opening of the bank layer and a part of an area with the bank layer.

Abstract: A magnetic sensor includes a semiconductor element, a lead frame, a bonding wire, and a package. The lead frame includes a die pad to which the semiconductor element is attached and an external connection lead. The bonding wire connects the external connection lead with the semiconductor element. The package seals the semiconductor element, the die pad, the external connection pad, and the bonding wire. The package is made of epoxy-based resin. The lead frame further includes a projecting portion extending from the die pad, the projecting portion is exposed from the package at a position different from a position of the external connection lead, and a partial surface of the projecting portion which contacts with the package is made of material having a higher ionization tendency than an ionization tendency of silver.

Abstract: The present disclosure provides semiconductor devices and manufacturing techniques in which a buried capacitive structure may be provided at the level of the buried insulating layer of an SOI device, thereby providing reduced process complexity compared to conventional strategies, while still preserving superior routing capabilities above the buried capacitive structures.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an upper surface, a semiconductor device mounted to the substrate, and a molding compound covering the lateral surface and the upper surface of the substrate and at least a portion of the semiconductor device. A surface of the semiconductor device is substantially coplanar with a surface of the molding compound.

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Abstract: A light emitting device includes a first electrode, a hole transporting layer in contact with the first electrode, a second electrode, an electron transporting layer in contact with the second electrode; and an emissive layer between the hole transporting layer and the electron transporting layer. The emissive layer includes a metal-assisted delayed fluorescent (MADF) emitter, a fluorescent emitter, and a host, and the MADF emitter harvests electrogenerated excitons and transfers energy to the fluorescent emitter.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

Abstract: A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings.