Abstract: The present invention relates to a plurality of host materials and an organic electroluminescent device comprising the same. By comprising a specific combination of a plurality of host compounds, the organic electroluminescent device according to the present invention provides excellent lifespan characteristics while maintaining high luminous efficiency.

Abstract: The invention provides a manufacturing method for TFT backplane, through forming an oxygen-containing a-Si layer on the buffer layer and an oxygen-free a-Si layer on the oxygen-containing a-Si layer so that when using a boron induced SPC to crystallize the a-Si thin film, the contact interface between the a-Si thin film and the buffer layer is the oxygen-containing a-Si layer; because the nucleation is not easy to occur in oxygen-containing a-Si layer during high temperature crystallization, the nucleation only occurs top-down in the boron doped layer on the upper surface of the a-Si thin film for good die quality and thin film uniformity to achieve improve crystalline quality and uniformity. The TFT backplane provided by the invention is made with simple process, wherein the crystalline quality and uniformity of the polysilicon layer is preferable, and can enhance the TFT performance and the driving effect.

Abstract: The disclosed embodiments include a method, apparatus, and computer program product for approximating multiphase flow reservoir production simulation. For example, one disclosed embodiment includes a system that includes at least one processor and memory coupled to the at least one processor, the memory storing instructions that when executed by the at least one processor performs operations that includes generating a set of pseudo-phase production relative permeability curves; receiving production rate history data; receiving simulation configuration parameters; performing flow simulation using the set of pseudo-phase production relative permeability curves; determining an optimal matching pseudo-phase production simulation result that best matches the production rate history data; and performing relative permeability inversion using signal processing analysis of production rate history data to approximate relative permeability curve descriptions with quantified uncertainty.

Abstract: The disclosed embodiments include a method, apparatus, and computer program product for approximating multiphase flow reservoir production simulation for ranking multiple petro-physical realizations.

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

Abstract: The present disclosure relates to semiconductor devices with gate-controlled energy filtering. One example embodiment includes a semiconductor device. The semiconductor device includes a first electrode, a second electrode, and a channel therebetween. The semiconductor device also includes a first interference structure located in the channel. Further, the semiconductor device includes a first gate for controlling a voltage over the first interference structure. The first interference structure is formed to induce a local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is: (1) aligned with a band structure in the semiconductor device to turn the semiconductor device on; and (2) misaligned with the band structure in the semiconductor device to turn the semiconductor device off.

Abstract: A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

Abstract: Changes in capillary pressure and relative permeabilities in reactive transport codes or reservoir simulators are formed by computer modeling. Based on continuum-scale hydraulic properties, the pore size distribution (PSD) is determined from a capillary pressure curve using the capillary tube concept. Changes in mineral volume through equilibrium or kinetic mineral reactions are then translated to changes in pore radii of the pore size distribution by selectively changing the radii of water occupied pores. The resulting new pore size distribution is converted back to an updated capillary pressure curve, which is then used for determining and forming models of total permeability and relative permeabilities at the continuum scale.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: An encapsulated device comprises: an organic optoelectronic component exhibiting at least one sensitive surface protected from oxygen and/or water vapor; and a multilayer encapsulation structure covering the sensitive surface, comprising at least one layer made of organic material interposed between first and second barrier layers made of nonmetallic inorganic material impermeable to oxygen and water vapor; wherein the barrier layers are made of a material chosen from a stoichiometric metal oxide, stoichiometric silicon oxide and a silicon oxynitride and produced by atomic layer deposition, and wherein the multilayer encapsulation structure also comprises at least one active layer containing a nonstoichiometric oxide exhibiting an oxygen deficiency, also interposed between the first and said second barrier layers. A process for encapsulating a component exhibiting a “sensitive” surface protected from oxygen and/or water vapor by producing a multilayer encapsulation structure is provided.

Abstract: An OLED substrate (1) and a preparation method therefor, an OLED panel, and an OLED display apparatus. An inter-layer insulation layer (12) is formed in an edge area of the OLED substrate (1), and a concave is formed on the surface of the inter-layer insulation layer (12), so that the lateral tensile-resistance strength of the inter-layer insulation layer (12) and a package substrate can be increased, i.e. increasing a lateral tensile-resistance force between the OLED substrate (1) and the package substrate, thereby improving the stability of the OLED panel, ensuring the sealing effect of the OLED panel and improving the service life of the OLED panel.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first gate overlying a first gate dielectric that in turn overlies a first channel. a second capacitor includes a second gate overlying a second gate dielectric that in turn overlies a second channel. The second gate dielectric has a different composition than the first gate dielectric. A capacitor interconnect is in electrical communication with the first capacitor and with the second capacitor.

Abstract: A method of manufacturing an organic light-emitting display apparatus using a light-blocking photoresist layer which minimizes damage to an intermediate layer, including an emission layer, during a process for manufacturing the organic light-emitting display apparatus.

Abstract: A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure.

Abstract: A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.

Abstract: Provided is an organic light-emitting display device. An organic light-emitting display device (OLED) includes: a substrate including at least three pixel regions arranged in a horizontal direction, a first electrode in each pixel region on the substrate, a bank surrounding each pixel region, and a power line in the horizontal portion at a lower side of each pixel region on the substrate, the power line being configured to supply a driving voltage to each pixel region.

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

Abstract: A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first contact member. The method also includes forming a first insulator layer having first and second contact holes, forming a second insulator layer on sidewalls of the first and second contact holes, filling the first and second contact holes with a first conductive material to form first and second contacts to the first and second gates, forming a third insulator layer on the first and second contacts, selectively etching the first insulator layer to form a third contact hole, and filling the third contact hole with a second conductive material to form a third contact to the first contact member.

Abstract: Provided is a method for forming a semiconductor structure. In embodiments, the method includes forming multiple channel nanosheets in multiple first stacks over a substrate. The channel nanosheets in the first stack define first stack cavities such that each pair of adjacent stacked channel nanosheets in the first stack is separated by one of the first stack cavities. The method further includes forming multiple channel nanosheets in a second stack over a substrate. The channel nanosheets in the second stack defining second stack cavities such that each pair of adjacent stacked channel nanosheets in the first second is separated by one of the second stack cavities. The method further includes filling the first stack cavities with a first gate dielectric material and filling the second stack cavities with a work function metal and a second gate dielectric material. The first gate dielectric material differs from the second gate dielectric material.