Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract: A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a discrete element part. The first semiconductor chip is arranged on the substrate and includes a first electrode group. The second semiconductor chip is arranged on the substrate and includes a second electrode group, at least one of electrodes included in the second electrode group being connected to at least one of electrodes included in the first electrode group via at least one bonding wire. The discrete element part is arranged on the substrate and under the at least one bonding wire.

Abstract: A composite substrate for a semiconductor includes a handle substrate 11 and a donor substrate bonded to a surface of the handle substrate 11 directly or through a bonding layer. The handle substrate 11 is composed of an insulating polycrystalline material, a surface 15 of the handle substrate 11 has a microscopic central line average surface roughness Ra of 5 nm or smaller, and recesses 6 are formed on the surface of the handle substrate.

Abstract: A gate metal structure and a forming method of the same are provided. The gate metal structure includes: a substrate and a copper metal layer; and a barrier layer disposed between the substrate and the copper metal layer, the barrier layer being formed of silicon oxynitride SiON or silicon oxide SiOx. By disposing a SiON or SiOx barrier layer between the substrate and the copper metal layer, conductivity and adhesion can be enhanced while reducing diffusion of copper when copper is used as the conductive metal layer material.

Abstract: A high electron mobility transistor includes a buffer region and a barrier region adjoining and extending along the buffer region, the buffer and barrier regions are formed from semiconductor materials having different band-gaps and form an electrically conductive channel from a two-dimensional charge carrier gas. A gate structure is configured to control a conduction state of the channel and includes an electrically conductive gate electrode, a first doped semiconductor region, a second doped semiconductor region, and a resistor. The first doped semiconductor region is in direct electrical contact with a first section of the gate electrode. The second doped semiconductor region is in direct electrical contact with a second section of the gate electrode. The first and second doped semiconductor regions form a p-n junction with one another. The first and second sections of the gate electrode are electrically coupled to one another by the resistor.

Abstract: A light emitting device in an embodiment includes first and second light transmissive insulators and a light emitting diode arranged between them. First and second electrodes of the light emitting diode are electrically connected to a conductive circuit layer provided on a surface of at least one of the first and second light transmissive insulators. Between the first light transmissive insulator and the second light transmissive insulator, a third light transmissive insulator is embedded which has at least one of a Vicat softening temperature of 80° C. or higher and 160° C. or lower and a tensile storage elastic modulus of 0.01 GPa or more and 10 GPa or less.

Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

Abstract: A method and structures are provided for implementing individual integrated circuit chip attach in a three dimensional (3D) stack. A plurality of hollow copper pillars is formed, and the hollow copper pillars are coated with lead free solder using vapor deposition.

Abstract: A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region. A field oxide film surrounds the first region in a plan view. A metal interconnect situated over a field oxide film. The metal interconnect formed of a metal having an electric resistivity at 25° C. of 40 ??·cm or more and 200 ??·cm or less. Further, the metal interconnect is repeatedly provided spirally in a direction along the edges of the first region. Further, the metal interconnect is electrically connected at the innermost circumference with the drain region, and is connected at the outermost circumference to the source region or a ground potential.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: The semiconductor module includes a pin that is connected to a semiconductor element; a pin wiring substrate that has a second metal film and a first metal film on the upper and lower surfaces, the first metal film and the second metal film being electrically bonded to the pin; solder that bonds the pin and the semiconductor element; a DCB substrate that has a third metal film and a fourth metal film on the upper and lower surfaces, the third metal film being bonded to a lower surface of the semiconductor element; and a first cooler that is connected to the fourth metal film. The ratio H/T of a height H of the solder to a distance T from the semiconductor element to the first metal film is equal to or greater than 0.2 and equal to or less than 0.7.

Abstract: A method and structures are provided for implementing individual integrated circuit chip attach in a three dimensional (3D) stack. A plurality of hollow copper pillars is formed, and the hollow copper pillars are coated with lead free solder using vapor deposition.

Abstract: In the case that a functional layer, made of a nitride of a group 13 element, is formed on a composite substrate including a sapphire body and a gallium nitride crystal layer disposed over the sapphire body, the deviation of the function is prevented. The composite substrate 4 includes a sapphire body 1A and a gallium nitride crystal layer 3 disposed over the sapphire body. Aa warpage of the composite substrate is in a range of not less than +40 ?m and not more than +80 ?m per 5.08 cm in length.

Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.

Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.

Abstract: The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.