Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.

Abstract: This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component is glued to the surface of a conductive layer, from which conductive layer conductive patterns are later formed. After gluing the component, an insulating-material layer, which surrounds the component attached to the conductive layer, is formed on, or attached to the surface of the conductive layer. After the gluing of the component, feed-throughs are also made, through which electrical contacts can be made between the conductive layer and the contact zones of the component. After this, conductive patterns are made from the conductive layer, to the surface of which the component is glued.

Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

Abstract: An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract: 4H SIC epiwafers with thickness of 50-100 ?m are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm?2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 ?s has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm?2. Epitaxial wafers with thickness of 50-100 ?m have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 ?m thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 ?m thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation.

Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

Abstract: A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the electrode of the semiconductor element to the distal end surface of the first lead; and a sealing resin covering the semiconductor element, at least a portion of the first lead, and the conductive bonding material.

Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

Abstract: An organic EL display device comprising: an anode; a cathode that is a metal film; a light-emitting layer between the anode and the cathode; and a sealing layer that covers a side of the cathode opposite a side on which the light-emitting layer is provided. An oxidation inhibiting layer and a cathode protecting layer are stacked between the cathode and the sealing layer. The oxidation inhibiting layer is closer to the light-emitting layer than the cathode protecting layer is.

Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Abstract: An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.

Abstract: A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.