Abstract: This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with sharp edges may improve the read and write speed and reduce the program and erase voltages in memory cells. It may also improve the gate control over the channel in tri-gate transistors and HEMTs. Methods to fabricate such devices are also disclosed.

Abstract: An ultraviolet light-emitting device with a lateral tunnel junction for hole injection includes a PN tunnel junction structure formed on a p-type layer at one side of an active region. The PN tunnel junction structure includes a p-type structure containing a plurality of alternately laminated p-AlGaN barrier layers and p-AlGaN well layers, and an n-type structure containing a plurality of alternately laminated n-AlGaN barrier layers and n-AlInGaN well layers, with the p-type structure facing the p-type layer. Both the p-type structure and the n-type structure have a plurality of projections extending from their surface. The n-type structure is formed on the p-type structure with the projections of the n-type structure fully filling void portions of the p-type structure.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches.

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.

Abstract: A CMOS image sensor unit and a method for fabricating the same are described. The image sensor unit includes a photodiode, a transfer gate, a reset gate, a source follower gate, a floating drain region between the transfer gate and the reset gate, and a PIP capacitor. The lower poly-Si electrode of the PIP capacitor is electrically connected with the floating drain region and the source follower gate to also serve as an interconnect between the floating drain region and the source follower gate. The fabrication method includes forming contact plugs on the floating drain region and the source follower gate, and then forming a PIP capacitor whose lower poly-Si electrode is connected with each contact plug.

Abstract: An image sensor device may include an interconnect layer having an opening extending therethrough, an image sensor IC within the opening and having an image sensing surface, and an IR filter aligned with the image sensing surface. The image sensor device may include an encapsulation material laterally surrounding the image sensor IC and filling the opening, and a flexible interconnect layer coupled to the interconnect layer opposite the image sensing surface.

Abstract: A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

Abstract: A semiconductor device includes: a semiconductor multi-layer structure which includes at least an electron traveling layer and an electron supply layer on a substrate, wherein the electron supply layer includes a first portion which contains Sb and has at least a portion doped with Te, and a second portion which is located closer to the electron traveling layer side than the first portion and has a lattice constant smaller than that of the first portion.

Abstract: A display device includes a display panel having a first substrate having a display region and a peripheral region surrounding the display region, a light emitting structure in the display region, a sealant in the peripheral region, the sealant including a first portion having a first width, and a second portion adjacent to the first portion and having a second width smaller than the first width, and a second substrate on the light emitting structure and the sealant, a body including an upper frame and a lower frame, the body receiving the display panel, and at least one function button at a first portion of the display device, at least a portion of the function button protruding out of the body, and the first portion of the sealant being disposed adjacent to the at least one the function button at the first portion of the display device.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A method for manufacturing a semiconductor device including a plurality of fin field-effect transistor (FinFET) devices, comprises forming a plurality of fins on a substrate, wherein a first portion of the fins corresponds to p-type field-effect transistors, and a second portion of the fins corresponds to n-type field-effect transistors, forming a plurality of gate electrodes on the plurality of the fins, growing a p-type doped epitaxial region at each of a plurality of source/drain regions between predetermined gate electrodes of the p-type field-effect transistors, and growing an n-type doped epitaxial region at one or more areas between gate electrodes of respective adjacent p-type field-effect transistors to create one or more p-n junctions electrically isolating the adjacent p-type field-effect transistors from each other.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

Abstract: A semiconductor light-emitting element includes, a first semiconductor layer, a second semiconductor layer, a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode provided on the second semiconductor layer. A side of the second electrode facing to the second semiconductor layer is composed of at least any one of silver and silver alloy. The second electrode has a void having a width of emission wavelength or less of the light-emitting layer in a plane of the second electrode facing to the second semiconductor layer.

Abstract: A semiconductor light-receiving device includes a substrate having a principal surface including first and second areas; a post disposed on the first area, the post including a semiconductor mesa; and a resin layer disposed on the second area in contact with a side surface of the post. The resin layer has, on a ray extending from a first point within the first area through a second point within the second area, a first thickness and a second thickness respectively at a third point and a fourth point that are located within the second area at different distances from the first point. The distance from the first point to the fourth point is larger than the distance from the first point to the third point. The first thickness is larger than the second thickness. The resin layer has a surface that monotonically changes from the first thickness to the second thickness.

Abstract: A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.

Abstract: One semiconductor device includes an active region extending in a first direction, and first, second, and third semiconductor pillars which are provided upright relative to a main surface of the active region and disposed side by side in succession in the first direction; and between the first semiconductor pillar and the second semiconductor pillar, a first gate insulating film in contact with a side surface of the first semiconductor pillar, a first gate electrode in contact with the first gate insulating film, a second gate insulating film in contact with a side surface of the second semiconductor pillar, a second gate electrode in contact with the second gate insulating film, and a first embedded insulating film located between the first and second gate electrodes; and between the second and third semiconductor pillars, a second embedded insulating film in contact with the side surfaces of the second and third semiconductor pillars.

Abstract: One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.