Abstract: In order to provide a light-emitting device having improved color rendering properties, a light-emitting device which uses a SiC fluorescent material comprises a first SiC fluorescent portion in which a donor impurity and an acceptor impurity are added and which is formed of a SiC crystal; a second SiC fluorescent portion which is formed of a SiC crystal in which the same donor impurity as the first SiC fluorescent portion and the same acceptor impurity as the first SiC fluorescent portion are added, and in which a concentration of the acceptor impurity is higher than the concentration of the acceptor impurity in the first SiC fluorescent portion and an emission wavelength is longer than that of the first SiC fluorescent portion; and a light-emitting portion that emits excitation light that excites the first SiC fluorescent portion and the second SiC fluorescent portion.

Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer. A thickness of a first portion of the barrier layer at the sidewall of the metal gate is substantially thinner than a thickness of the barrier layer at the bottom of the metal gate. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate trench in an ILD, forming a barrier layer in a bottom and a sidewall of the metal gate trench, removing a first portion of the barrier layer at the sidewall of the metal gate trench, and forming a work function metal layer conforming to the barrier layer.

Abstract: A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

Abstract: The present invention relates to a thin film transistor array substrate and a method of manufacturing the same.

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract: A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region.

Abstract: A light-emitting device includes a light-emitting element emitting blue light, a green phosphor emitting green light when being excited by the blue light, and a red phosphor emitting red light when being excited by the blue light. An emission spectral peak wavelength of the green light emitted by the green phosphor is greater than or equal to 520 nm and less than or equal to 540 nm.

Abstract: A semiconductor substrate has an element portion and a termination portion located on an outer side of the element portion. A first electrode layer is provided on a first surface of the semiconductor substrate. A second electrode layer is provided on a second surface of the semiconductor substrate in an upper portion of the element portion. An interlayer insulation film is provided on the second surface of the semiconductor substrate. The interlayer insulation film has: an element insulation portion that provides insulation between a part of the element portion of the semiconductor substrate and the second electrode layer; and a termination insulation portion covering a termination portion of the semiconductor substrate. The termination insulation portion includes a high dielectric constant film that is higher in dielectric constant than the element insulation portion.

Abstract: A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer deposited in a gate trench and on a semiconductor portion of the substrate. At least one workfunction layer has an arrangement of first and second workfunction granular portions on an upper surface of the high-k layer to define a workfunction of the semiconductor device. The arrangement of first and second workfunction granular portions define a granularity of the at least one workfunction layer. A gate contact material fills the gate trench, wherein the high-k layer has a concentration of oxygen vacancies based on the granularity of the at least one work function metal layer so as to reduce the variation in the threshold voltage.

Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.

Abstract: The present invention provides a method for producing a template for epitaxial growth, the method including: a surface treatment step of dispersing Ga atoms on a surface of a sapphire substrate; and an AlN growth step of epitaxially growing an AlN layer on the sapphire substrate, wherein in a Ga concentration distribution in a depth direction perpendicular to the surface of the sapphire substrate in an internal region of the AlN layer excluding a near-surface region up to a depth of 100 nm from the surface of the AlN layer, which is obtained by secondary ion mass spectrometry, a position in the depth direction where the Ga concentration takes the maximum value is present in a near-interface region located between the interface of the sapphire substrate and a position at 400 nm spaced apart from the interface to the AlN layer side, and the maximum value of the Ga concentration is 3×1017 atoms/cm3 or more and 2×1020 atoms/cm3 or less.

Abstract: A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium.

Abstract: System on chips (SoCs) of a microprocessor electrically connected with electronic memory devices and/or optically connected with a optical memory device are disclosed along with various embodiments of building block of the microprocessor and the electronic memory devices, wherein the microprocessor can comprise digital unit and/or neural networks based unit.

Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.

Abstract: The semiconductor layer sequence includes an n-conductive layer, a p-conductive layer and an active zone located therebetween. The active zone comprises N quantum wells with N?2. At a first working point (W1) at a first current density, the quantum wells have a first emission wavelength and, at a second working point (W2) at a second current density, a second emission wavelength. At least two of the first emission wavelengths differ from one another and at least some of the second emission wavelengths differ from the first emission wavelengths. The first current density is smaller than the second current density and the current densities differ from one another at least by a factor of 2.

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract: A quantum dot light emitting diode, including a first electrode and a second electrode, a quantum dot light emitting layer disposed between the two electrodes, including at least a red quantum dot, a green quantum dot and a blue quantum dot, and a black matrix at least disposed among the red quantum dot, the green quantum dot and the blue quantum dot; one of the first electrode and the second electrode that is located on a light exiting side is at least a transparent electrode. With the quantum dot light emitting diode, a full-color display can be realized, and the aperture ratio of pixels can be effectively enhanced. There are further disclosed a manufacturing method of the quantum dot light emitting diode and a display device.

Abstract: A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.

Abstract: A stacked optoelectronic packaged device includes a plurality of stacked components within a package material having a package body providing side walls and a bottom wall for the package, and a lid which seals a top of the package. The stacked components include a first cavity die having a top surface and a bottom surface including at least one through-channel formed in the bottom surface. A bottom die has a top surface including at least one electrical trace and a light source die thereon. At least one of the through-channels of the first cavity die are aligned to the electrical trace, and the first cavity die is bonded to the bottom die with the electrical trace being within the through-channel and not contacting the first cavity die to provide a vacuum sealing structure. A photodetector (PD) is optically coupled to receive the light originating from the light source.