Abstract: Disclosed are a method and apparatus for identifying peripheral configuration of server, a method and apparatus for laying out peripheral silkscreen, and a server.

Abstract: One aspect of the instant application can provide a networking device. The networking device can include a set of Compute Express Link (CXL) ports, a set of non-CXL ports, a set of bridge circuits associated with the set of CXL ports, and an interconnect. A respective bridge circuit can include a packet-conversion subcircuit to convert a CXL packet received at a corresponding CXL port to a customized packet and a protocol-conversion subcircuit to convert a CXL protocol to a customized protocol implemented by the networking device. The interconnect can switch customized packets among the CXL and non-CXL ports based on the customized protocol.

Abstract: Disclosed are an asynchronous FIFO read/write control method and system, and an electronic device, belonging to the technical field of data read/write technology. The asynchronous FIFO read/write control method comprises: parsing data received by a front-end interface to obtain a data packet length and valid video data; determining an almost empty threshold of a first FIFO queue and a second FIFO queue according to the data packet length, and writing the valid video data into the first FIFO queue and the second FIFO queue in a ping-pong manner; determining a minimum time interval of FIFO readings according to a sending time sequence of a back-end interface, and reading data from the first FIFO queue and the second FIFO queue in the ping-pong manner according to the almost empty threshold and the minimum time interval, so as to output the read data through the back-end interface.

Abstract: Provided is an artificial intelligence (AI) computing device applied to an industrial automation system. The AI computing device is connected to a field bus via a field bus interface and is communicated with a controller. The AI computing device processes data sent by the controller by using a built-in AI computing architecture, analyzes the data, and sends the analysis result to the controller. Also provided are a corresponding method and apparatus, an engineer station, and an industrial automation system.

Abstract: Shutdown intervals between nodes of a dependency tree are determined. The dependency tree represents a system to be shut down and the nodes represent system components of the system. The determining the shutdown intervals includes calculating, for a pair of nodes of the dependency tree, a shutdown interval. The calculating is based on a relationship between the pair of nodes. The calculating is repeated for a plurality of pairs of nodes to obtain a plurality of shutdown intervals. The plurality of shutdown intervals is used in a shutdown of the system components. At least one system component represented by at least one node on a higher node level of the dependency tree is to be shut down prior to at least one other system component represented by at least one other node on a lower node level of the dependency tree.

Abstract: A semiconductor device includes: a plurality of ports exchanging data with each other in an interface; and an interface controller including a link training and status state machine (LTSSM), configured to execute link-up, setting a plurality of lanes to the plurality of ports, and a memory configured to store a sequence, in which the LTSSM succeeding in the link-up executes states, as a reference sequence. The interface controller changes at least one of the PHY parameters when a calibration operation of adjusting the PHY parameters starts until a sequence of the states, executed by the LTSSM to complete the link-up, matches the reference sequence.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a boot operation of the data storage device is initiated, the controller retrieves a relevant boot file from the memory device to boot the data storage device with. The relevant boot file to be retrieved from a plurality of boot files may be determined by a write temperature corresponding to the temperature of when the boot file was programmed to the memory device and a read temperature of the boot file during the boot operation. Each boot file of the plurality of boot files is programmed using different programming parameters in order to cover a range of possible retention levels.

Abstract: A bridge device for bridging a host device and a data storage device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface. The second transmission interface is coupled to the first transmission interface through a bus. The first transmission interface operates in a slave mode and the second transmission interface operates in a master mode. The first transmission interface and the second transmission interface generate multiple transfer data chunks in compliance with a common bridge transfer format to perform transfer operations in dual directions for respectively transferring a command and data between a host device and a data storage device.

Abstract: A pair of compute nodes, each having a separate PCIe root complex, are interconnected by a PCIe Non-Transparent Bridge (NTB). An instance of a NTB monitoring process is started for each root complex, and the CPU affinity of the NTB monitoring processes are set to cause each NTB monitoring process to be executed on CPU resources of each respective CPU root complex. The NTB monitoring process on a given root complex is allowed to sleep until a triggering event occurs that causes the NTB monitoring process to wake and determine the state of the NTB. One such triggering event is a failure of an atomicity algorithm on the compute node to obtain a lock on peer memory in connection with implementing an atomic read operation on the peer memory over the NTB.

Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

Abstract: A method, circuit and apparatus for protecting power supply of a peripheral component interconnect express (PCIE) card, and a medium are provided card hardware design. When the PCIE card is not completely inserted into a slot of a server, a first power supply and a second power supply are controlled to release electric energy, a controller is controlled to turn off a first MOS transistor, and a load is charged with the electric energy released by the second power supply. When the PCIE card is completely inserted into the slot of the server, a PRSNT #signal is generated, a second MOS transistor is controlled to be turned on, and the controller is controlled to turn on the first MOS transistor. When the PCIE card is not completely pulled out, the second MOS transistor is controlled to be turned off, and the controller is controlled to turn off the first MOS transistor.

Abstract: A method includes removably coupling a projectile interface of a dongle to a dongle interface of a projectile. The method also includes loading a dongle code from the dongle onto the projectile. The dongle code identifies a pulse repetition frequency (PRF) code to be recognized by the projectile. The dongle code may be unique to an operator of the projectile. The method may further include, prior to loading the dongle code onto the projectile, loading an operator code onto the projectile, where the dongle code is loaded onto the projectile in response to the projectile authorizing the operator code. There may be a limited number of uses of the dongle code with different projectiles, and/or there may be a limited amount of time for using the dongle code. A companion electronic device may be used to authenticate the dongle.

Abstract: A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.

Abstract: A power source selection system can include a primary source line configured to be connected to a primary source having a primary voltage, a backup source line configured to connect to a backup source having a backup voltage, and a voltage divider and limiter connected to the primary source line to receive the primary voltage and to provide an sense signal on a sense line. The system can include a NAND gate connected to the voltage divider and limiter to receive the sense signal. The NAND gate can be configured to provide a gate signal to a gate line based on the sense signal. The system can include a switchover circuit connected to the backup source line and the gate line to receive the backup voltage and the gate signal. The switchover circuit can be configured to output the backup voltage to a switch line in a first state, and to prevent backup voltage to the switch line in a second state.

Abstract: The disclosed technology includes systems and methods for receiving field data associated with industrial equipment from one or more field devices operating under an event-based data transmission schema to, storing the field data at a remote computing system, receiving a request for the field data from an industrial data polling system operating under a polling protocol, and transmitting the field data, from the remote computing system and to the industrial data polling system, as a polling protocol reply.

Abstract: Declarative provisioning of storage, including: identifying one or more policies associated with a storage object; determining, in dependence upon at least the one or more policies, a storage configuration for the storage object; and provisioning, in accordance with the storage configuration, storage that implements the storage object.

Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

Abstract: An electronic device includes a memory and a processor. The processor acquires a platform management profile, the platform management profile including information defining one or more platform management policies. The processor provides the platform management profile to platform management drivers executing on one or more electronic devices, the platform management profile being configured so that each of the platform management drivers can extract the one or more platform management policies from the platform management profile and use the one or more platform management policies for controlling operating states of elements (e.g., functional blocks, devices, etc.) of the respective electronic device.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.