Abstract: Described herein are techniques for managing failover in a data center environment interconnected using an internet small computer systems interface (iSCSI) communication protocol, the techniques including receiving, at a host and from a kernel driver, an asynchronous message comprising an indication of a failed path associated with a first node having a first port, a list of internet protocol (IP) addresses associated with a plurality of failover paths including a first failover path associated with a second node having a second port, and an expiration. The techniques further including performing, by the host and before the expiration, a first input/output (I/O) operation on the second port associated with the second node. The techniques further including performing, by the host and after the expiration, a second I/O operation on the first port of the first node.

Abstract: An electronic part including an integrated circuit and a memory, the integrated circuit including a first clock terminal to which a clock signal is inputted, a first data terminal via which a first serial data signal is inputted and outputted, a second clock terminal via which the clock signal is outputted to the memory, a second data terminal via which a second serial data signal is inputted and outputted from and to the memory, and a first interface circuit including a control circuit that controls the communication state of the integrated circuit to be a first communication state in which the first serial data signal inputted to the first data terminal is outputted as the second serial data signal via the second data terminal or a second communication state in which the second serial data signal inputted to the second data terminal is outputted as the first serial data signal via the first data terminal.

Abstract: Apparatus, systems, methods, and articles of manufacture to manage power of deep learning accelerator systems are disclosed. An example apparatus includes a power manager and a power controller. The power manager is to generate a power table to allocate power frequencies between an accelerator and memory based on a ratio of compute tasks and bandwidth tasks in a first workload; update the power table based on a request to at least one of add a second workload or remove the first workload; and determine an index into the power table. The power controller is to determine a power consumption based on the power table; determine whether to update the index based on a power budget and the power consumption; and allocate power to the accelerator and the memory according to the power table.

Abstract: A method includes mapping a monitor setting to a shortcut key associated with a human interface device, and translating the monitor setting of a first monitor into binary data based on a lookup table. The method may also generate a human interface device report; embed the binary data in the human interface device report, and store the human interface device report with the binary data in the human interface device. The method may also detect invocation of the shortcut key using the human interface device, match an identifier in the human interface device report associated with the shortcut key; and retrieve the binary data based on the identifier. The method may also transmit the binary data to a second monitor.

Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.

Abstract: This document describes techniques and systems that enable a smartphone-based radar system for determining user intention in a lower-power mode. The techniques and systems use a radar field to enable the smartphone to accurately determine the presence or absence of a user and further determine the intention of the user to interact with the smartphone. Using these techniques, the smartphone can account for the user's nonverbal communication cues to determine and maintain an awareness of users in its environment, and only respond to direct interactions once a user has demonstrated an intention to interact, which preserves battery power. The smartphone may determine the user's intention by recognizing various cues from the user, such as a change in position relative to the smartphone, a change in posture, or by an explicit action, such as a gesture.

Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.

Abstract: A method for managing frames in a computer providing an operational function and a gateway function between two communication buses in order to transmit messages from a transmitter to a receiver, including: receiving messages from a transmitter via the first bus; storing the received messages; triggering an interrupt of the execution of an operational program causing the processing of the stored messages for transmission to the receiver via the second bus; deactivating the interrupt in order to continue the execution of the functional program, after the expiration of a duration and at the end of the processing of a message currently being processed during the expiration; and, triggering a new interrupt at the end of a timeout of a duration of the execution of the operational program causing the processing of messages stored for transmission to the receiver via the second bus to continue.

Abstract: A system and method for power distribution are disclosed. A processor detects a storage device having a scalable interface, where the scalable interface is for transferring data between a host device and the storage device. The processor determines power requirement of the storage device based on a signal from the scalable interface. At least one power supply unit coupled to the processor provides power to the storage device based on the determined power requirement.

Abstract: A port controller circuit implements monitoring and detection of power path short failures by regulating the control voltage to the power switches during the on-state of the power switches. A failure condition is indicated when the control voltage to a power switch is regulated to a voltage level outside of a permissible range. The port controller circuit implements real-time monitoring where a short within the power path can be detected while the power path is enabled and the fault condition can be used to disable other port controller circuits in a multi-port system. In one embodiment, a port controller circuit includes a pair of back-to-back transistors forming the power path and the real-time fault detection scheme is applied to control each transistor independently to determine if either transistor has a fault condition.

Abstract: Systems, methods, and apparatus increase the number of slave devices that can be connected to a serial bus. The bus protocol may be an RFFE protocol, an SPMI protocol, an I3C protocol or another protocol usable on a serial bus. In various aspects of the disclosure, a method performed at a device coupled to a serial bus includes receiving a first datagram at a slave device coupled to a serial bus, where the first datagram includes a 4-bit broadcast address indicative of a broadcast datagram, a first command directed to an invalid register address, and a payload, determining an encapsulation protocol associated with the invalid register address, and responding to a second command carried in the payload when an 8-bit slave address in the payload matches an 8-bit slave identifier allocated to the slave device.

Abstract: In some examples, a transport agnostic source includes a streaming device to stream video on diverse transport topologies including isochronous and non-isochronous transports. In some examples, a transport agnostic sink includes a receiving device to receive streamed video from diverse transport topologies including isochronous and non-isochronous transports.

Abstract: A memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or special-purpose controller), and at least one interface device configured to communicate input and output data for the memory module. The input and output data bypasses at least one processor (e.g., a central processing unit) of a computing device in which the memory module is installed. And, the at least one interface device can be configured to communicate the input and output data to at least one other memory module in the computing device. Also, the memory module can be one module in a plurality of memory modules of a memory module system.

Abstract: In some examples, a system includes a memory resource, a communication channel to allow a bus mastering capable device to access the memory resource, and a controller to block the system from responding to a request from the bus mastering capable device for accessing the memory resource until the controller has authorized the bus mastering capable device.

Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.

Abstract: A request to retrieve data from a memory device of a memory sub-system can be received from a machine learning (ML) framework executing on a host system, where the data comprises a plurality of logical partitions. A set of parallel I/O threads can be initiated to retrieve the data from the memory device, where each I/O thread of the set of parallel I/O threads retrieves a different portion of the data from a different corresponding logical partition and stores the different portion of the data in a I/O buffer of a set of I/O buffers corresponding to the set of I/O threads in parallel. The different portion of the data can be successively provided from each I/O buffer to the ML framework, where the set of parallel I/O threads is to continually retrieve the data from the memory device until all of the data from the logical partitions has been provided to the ML framework.

Abstract: Techniques are described for the creation and use of input/output (I/O) filters used to perform actions relative to I/O requests passing through an I/O proxy device of a computer system. A computer system includes one or more hardware processing elements (for example, one or more central processing units (CPUs), graphics processing units (GPUs), or other types of processing elements), one or more data storage devices (for example, hard-disk drives, solid-state drives (SSDs), network-accessible block storage devices, and so forth), and an I/O proxy device that is interposed between at least one of the hardware processing elements and at least one of the one or more data storage devices. The interposition of an I/O proxy device between hardware processing elements and data storage devices enables the I/O proxy device to participate in the I/O data path, for example, to receive I/O messages and to perform various actions relative to such messages.

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.

Abstract: A storage device comprises a controller and a plurality of nonvolatile memory devices. Maintenance conditions of the nonvolatile memory devices are monitored internally by the storage device. Upon determining that a maintenance condition is satisfied, the storage device notifies an external host. The controller may perform the maintenance operations on the plurality of nonvolatile memory devices with little disruption to the host and assure data is reliably maintained by the nonvolatile memory devices.