Abstract: The embodiments of the disclosure provide an Application (APP) preloading method and device, a storage medium and a terminal. The method includes that: when an APP preloading event is detected to be triggered, an APP to be preloaded is determined; whether a first APP which is being started in foreground exists or not is judged; and if NO, the APP to be preloaded is preloaded. According to the application, with adoption of the technical solution, not only low speed and non-fluency, caused by preloading the APP, for starting of the APP in foreground may be effectively avoided, but also a speed of preloading the APP to be preloaded may be effectively increased, so that a speed of starting the APP to be preloaded may be increased.

Abstract: A printed circuit board comprises: a network controller; a memory controller; a heterogeneous processor; a field-programmable gate array (FPGA); and a non-volatile-media controller. The memory controller comprises: a fabric controller component configured to communicate with the network controller, the heterogeneous processor, the FPGA, and the non-volatile-media controller; and a media controller component configured to manage access relating to data stored in a volatile memory media. The FPGA is configured to perform computations relating to data stored via the non-volatile-media controller. The heterogeneous processor is configured to perform computation tasks relating to data stored via the memory controller. The printed circuit board is configured to be plugged in to a rack with a plurality of other plugged-in circuit boards.

Abstract: Disclosed is an electronic device. According to an embodiment disclosed in this specification, an electronic device may include a first interface, a second interface, an input device generating a specified signal associated with disconnection of a first external electronic device, and a processor operatively connected to the first interface, the second interface, and the input device. The processor may be configured to receive power from the first external electronic device through the first interface in a state where the first external electronic device is connected to the first interface and a second external electronic device is connected to the second interface, and to receive power from the second external electronic device through the second interface when receiving the specified signal generated by the input device. Other various embodiments as understood from the specification are also possible.

Abstract: A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability.

Abstract: An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected (e.g., serially) multiplier-accumulator circuits and/or one or more rows of interconnected (e.g., serially) multiplier-accumulator circuits. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one multi-bit MAC execution pipeline, wherein each pipeline includes a plurality of interconnected (e.g., serially) multiplier-accumulator circuits. Each control/configure circuit may include one or more (or all) of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s), (ii) a configurable accumulation data path for the ongoing/accumulating MAC accumulation totals generated by the MACs during an execution sequence, and (iii) a configurable output data path for the output data generated by execution sequence (i.e.

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: A semiconductor integrated circuit includes a central processing unit, a hardware function block that outputs a plurality of hardware signals to be transmitted to an external device independently of the central processing unit, a virtual general purpose input/output (GPIO) finite state machine that transforms the plurality of hardware signals to a virtual GPIO payload, and an I3C communication block that transmits the virtual GPIO payload to the external device through a serial data line and a serial clock line.

Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A system may include an air mover configured to drive a flow of air, a heat-generating component in a path of the flow of air, an assembly comprising heat-rejecting media and a thermoelectric cooling apparatus thermally coupled to the heat-rejecting media and arranged such that the heat-rejecting media is in the path of the flow of air between the air mover and the heat-generating component, and a thermal control system communicatively coupled to the thermoelectric cooling apparatus and configured to control an electrical parameter applied to the thermoelectric cooling apparatus in order to create a temperature gradient across the thermoelectric cooling apparatus, such that when the electrical parameter is applied to the thermoelectric cooling apparatus, heat is transferred from the flow of air to the thermoelectric cooling apparatus via the heat-rejecting media.

Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

Abstract: A controller of a storage device is described for handling communications with a host device. In some examples, the storage device includes a wide port comprising a plurality of phys. The wide port is configured to receive, via a first phy of the plurality of phys, a signal. The controller is configured to select, based on a respective power factor associated with each respective phy of the plurality of phys and a respective performance factor associated with each respective phy of the plurality of phys, a second phy of the plurality of phys to utilize for performing an operation associated with the received signal. In such examples, the wide port is further configured to perform, using the second phy, the operation associated with the received signal.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: Examples in this application disclose an operation accelerator, a switch, and a processing system. One example operation accelerator includes a shunt circuit directly connected to a first peripheral component interconnect express (PCIe) device through a PCIe link. The shunt circuit is configured to receive first data sent by the first PCIe device through the PCIe link, and transmit the first data through an internal bus. A first address carried in the first data is located in a first range. In some examples of this application, the first PCIe device directly communicates with the operation accelerator through the shunt circuit in the operation accelerator.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash storage. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: receiving a host write command from a host side; determining whether the flash storage needs to enter a hibernate state based on at least information regarding a length of data that has been programmed into the flash storage and/or a quantity of host write commands that have been executed after executing the host write command; and instructing the flash storage to enter the hibernate state when the length of data and/or the quantity of host write command meets a triggering condition.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: A method for performing dynamic throttling control with aid of configuration setting and associated apparatus such as a host device, a data storage device and a controller thereof are provided. The method includes: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Abstract: Described herein are techniques for managing failover in a data center environment interconnected using an internet small computer systems interface (iSCSI) communication protocol, the techniques including receiving, at a host and from a kernel driver, an asynchronous message comprising an indication of a failed path associated with a first node having a first port, a list of internet protocol (IP) addresses associated with a plurality of failover paths including a first failover path associated with a second node having a second port, and an expiration. The techniques further including performing, by the host and before the expiration, a first input/output (I/O) operation on the second port associated with the second node. The techniques further including performing, by the host and after the expiration, a second I/O operation on the first port of the first node.