Patents Examined by Nishath Yasmeen
  • Patent number: 10411174
    Abstract: A semiconductor light-emitting device including at least a substrate, a reflector having a concave cavity, and an optical semiconductor element, wherein the reflector is formed of a resin composition containing an inorganic substance; in a spectrum obtained when the reflector is measured by an X-ray diffraction method using CuK? radiation (wavelength=1.5418 A), an intensity ratio (P1/P2) of a peak intensity P1 of the highest intensity diffraction peak in a range of diffraction angle 2? of 0° to 24° to the peak intensity P2 of the highest intensity diffraction peak in a range of diffraction angle 2? of more than 24° to 70° is 0.01 or more and 1.0 or less; and an ash content of the reflector is 60% by mass or more. A semiconductor light-emitting device and an optical-semiconductor-mounting substrate, including a reflector having an extremely high light reflection property and excellent dimensional stability.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: September 10, 2019
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Aki Kimura, Katsuya Sakayori, Kei Amagai, Satoru Kanke, Toshiyuki Sakai, Toshimasa Takarabe, Makoto Mizoshiri
  • Patent number: 10403678
    Abstract: A ?LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Christopher Percival
  • Patent number: 10403579
    Abstract: A semiconductor device includes a semiconductor chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads, a passivation layer disposed on the connection member, and an under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Ul Lee, Jin Su Kim, Young Gwan Ko
  • Patent number: 10396008
    Abstract: A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Takuya Kadoguchi, Yuji Hanaki, Syou Funano, Shingo Iwasaki, Takanori Kawashima
  • Patent number: 10388599
    Abstract: Processes for manufacturing cellulose based integrated circuitry constructions are provided, the processes can include providing a first substrate having a plurality of vias; providing a first conductive material to the one surface of the substrate; providing adhesive to the other surface; providing a monolithic electronic component to the other surface; providing a second conductive material to the other surface and the monolithic electronic component; providing a backing material to the other surface of the substrate; and providing a second substrate to the backing material to form the construction.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 20, 2019
    Inventors: Andrew DePaula, Samuel Riemersma, Charles Harral
  • Patent number: 10361401
    Abstract: The present invention discloses an organic electroluminescent display device and a display apparatus, wherein the organic electroluminescent display device employs an optical film lamination as a base substrate or a packaging cover plate, the optical film lamination includes a circular polarizer film, a water-oxygen resistant film and a color resistant film that are located on a supporting substrate, thus it has an antireflection function, a good water-oxygen resistance as well as a full-color display function, so that not only the problem of fussy process and high cost of an OLED display device caused by film application can be solved, but also the problem that the thickness of a flexible OLED display device is increased and thus the device is difficult to be rolled up due to film application is avoided; also, the OLED display device has the advantages of being lighter and thinner and having a better display effect, etc.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 23, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiliang Wang, Chungchun Lee, Xiaoguang Xu, Qinghui Zeng
  • Patent number: 10355129
    Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Chao Feng Yeh, TianChen Dong
  • Patent number: 10340229
    Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Georg Talut
  • Patent number: 10326030
    Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive block having a front side and a back side, a wave guide region, and a light sensing region. The wave guide region is positioned over the back side of the semiconductive block and having a core layer. The wave guide region is configured to guide an incident light. The light sensing region is positioned in the semiconductive block, having a multi-junction photodiode. The light sensing region is configured to sense emission lights from the wave guide region.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 18, 2019
    Assignee: PERSONAL GENOMICS, INC.
    Inventor: Teng-Chien Yu
  • Patent number: 10319721
    Abstract: Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Soon-Cheon Seo
  • Patent number: 10304961
    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shuhei Nagatsuka, Yutaka Shionoiri
  • Patent number: 10297727
    Abstract: A converter material includes a porous inorganic matrix material having a multiplicity of pores. A multiplicity of inorganic nanoparticles are applied on the surface of the matrix material. The nanoparticles are suitable for converting electromagnetic radiation in a first wavelength range into electromagnetic radiation in a second wavelength range. A method for producing such a converter material and an optoelectronic component that includes such a converter material are furthermore specified.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: May 21, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Ion Stoll, Britta Göötz
  • Patent number: 10283639
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Patent number: 10276793
    Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Jung, Youn-Seon Kang
  • Patent number: 10276694
    Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 30, 2019
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Ha-Jin Lim, Hyeong-Joon Kim, Nae-In Lee
  • Patent number: 10269877
    Abstract: A display device is disclosed. In one aspect, a plurality of pixels are formed in a display area, and the pixels include a first pixel including a thin film transistor (TFT). The display device includes a test unit formed in a peripheral area surrounding the display area, and the test unit includes a test transistor configured to measure a characteristic of the TFT included in the first pixel. The display device also includes a first insulating layer formed over the test transistor and the display area, and a plurality of dummy contact holes are formed in the first insulating layer and the test unit.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Won Mi Hwang
  • Patent number: 10269933
    Abstract: A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 10263116
    Abstract: For improved high-definition of liquid crystal display devices and the use thereof in bright places, luminance of backlights is being increased. Thus, when a light-shielding layer is employed for suppressing a light leakage current, characteristic fluctuations of transistors are caused, which may result in showing faulty display. In a dual-gate thin film transistor having a floating light-shielding layer, the layout is designed in such a manner that the film thickness of the insulating layer is equal to or more than 200 nm and equal to or less than 500 nm and that Sg/Sd becomes 4.7 or more, provided that an opposing area between the light-shielding layer and a drain region in a place at the outermost side of the active layer is Sd and the opposing area between the light-shielding layer and the gate electrode is Sg.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 16, 2019
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Nobuya Seko, Yoshikazu Hatazawa, Hiroyuki Sekine
  • Patent number: 10254244
    Abstract: A vertical biosensor includes a substrate and a source disposed on the substrate. A bottom spacer is disposed on the source. A chamber is disposed on the bottom spacer. A sensing gate dielectric is disposed on side and bottom surfaces of the chamber. A fin channel is disposed on opposite sides of the chamber along a direction parallel to an upper surface of the substrate facing the chamber. A back gate dielectric is disposed on the fin channel. A drain is positioned above the fin channel along a direction orthogonal to an upper surface of the substrate. A thickness of the back gate dielectric is greater than a thickness of the sensing gate dielectric.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10242981
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre