Patents Examined by Nishath Yasmeen
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Patent number: 12218037Abstract: A semiconductor device with front and back surfaces, and a side surface having first and second sides opposite to each other, and third and fourth sides opposite to each other. The semiconductor device includes a plurality of circuit boards surrounded by the first to fourth sides, the circuit boards each including an insulating board and a conductive plate, a first lead frame including a first terminal portion extending upward and being bent toward the first side, a second lead frame including a second terminal portion extending upward and being bent toward the second side, and a resin-filled portion provided in a first gap between the first terminal portion and the second terminal portion, the resin-filled portion having a concave portion recessed in a direction from the front surface toward the back surface so that an insulating insertion member is inserted into the concave portion.Type: GrantFiled: February 14, 2024Date of Patent: February 4, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hisato Inokuchi
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Patent number: 12198979Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.Type: GrantFiled: November 9, 2023Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
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Patent number: 12199005Abstract: A silicon nitride circuit board includes a silicon nitride substrate, a first copper layer over one surface of the silicon nitride substrate, and a second copper layer over the other surface of the silicon nitride substrate, in which a fracture toughness value Kc of the silicon nitride substrate is equal to or more than 5.0 MPa·m0.5 and equal to or less than 10.0 MPa·m0.5, and when a coefficient of linear expansion of the silicon nitride substrate is ?B (/° C.), a Young's modulus of the silicon nitride substrate is EB (GPa), a coefficient of linear expansion of the first copper layer is ?A (/° C.), and a coefficient of linear expansion of the second copper layer is ?C (/° C.), each of a heat shock parameter HS1 and a heat shock parameter HS2 is equal to or more than 1.30 GPa and equal to or less than 2.30 GPa.Type: GrantFiled: March 26, 2020Date of Patent: January 14, 2025Assignee: DENKA COMPANY LIMITEDInventors: Seiji Yano, Katsunori Terano
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Patent number: 12191394Abstract: A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.Type: GrantFiled: December 7, 2021Date of Patent: January 7, 2025Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventor: Huilong Zhu
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Patent number: 12185633Abstract: A MEMS device having a body with a first and a second surface, a first portion and a second portion. The MEMS device further has a cavity extending in the body from the second surface; a deformable portion between the first surface and the cavity; and a piezoelectric actuator arranged on the first surface, on the deformable portion. The deformable portion has a first region with a first thickness and a second region with a second thickness greater than the first thickness. The second region is adjacent to the first region and to the first portion of the body.Type: GrantFiled: June 6, 2023Date of Patent: December 31, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Domenico Giusti, Carlo Luigi Prelini
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Patent number: 12176274Abstract: A semiconductor package comprises a first die thermally coupled to a first thermally conductive device. The first thermally conductive device has a first surface exposed to an exterior of the semiconductor package. The package comprises a second die thermally coupled to a second thermally conductive device, the second thermally conductive device having a second surface exposed to an exterior of the semiconductor package. The first and second dies are positioned in different horizontal planes.Type: GrantFiled: November 26, 2018Date of Patent: December 24, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Tianyi Luo
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Patent number: 12176298Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.Type: GrantFiled: December 8, 2020Date of Patent: December 24, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Steven Kummerl, Kurt Peter Wachtler
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Patent number: 12178031Abstract: Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.Type: GrantFiled: December 16, 2021Date of Patent: December 24, 2024Assignee: SOCIONEXT INC.Inventor: Yoshinobu Yamagami
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Patent number: 12159817Abstract: A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.Type: GrantFiled: July 9, 2021Date of Patent: December 3, 2024Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Sung Chul Joo, Ulf Hakan Andre
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Patent number: 12161031Abstract: A display device includes a thin film transistor layer including a first interlayer insulation film, a first wiring layer, a second interlayer insulation film, a second wiring layer, a third interlayer insulation film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; and a first damming wall in a frame area separated from the first and second planarization film in a display area by a first slit. There is provided a fourth interlayer insulation film between the third and fourth wiring layer. The fourth interlayer insulation film covers an edge of either one or both of a first frame line and a second frame line as the third wiring layer in a region where the first frame line is located opposite the second frame line in a plan view, the edge facing the display area and being exposed in the first slit.Type: GrantFiled: October 21, 2019Date of Patent: December 3, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Patent number: 12155012Abstract: A nanowire optical device includes: a photonic crystal body having a planar shape and provided on a base part; an optical waveguide by a line defect in which a plurality of defects including a part without grating elements of the photonic crystal body are linearly arrayed; a trench formed in a waveguide direction in the optical waveguide; a nanowire made of a semiconductor and arranged in the trench; an n-type region formed on one end side of the nanowire; a p-type region formed on the other end side of the nanowire; an active region provided to be interposed between the n-type region and the p-type region in the nanowire; a first electrode connected to the n-type region; and a second electrode connected to the p-type region.Type: GrantFiled: October 31, 2019Date of Patent: November 26, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Masato Takiguchi, Masaya Notomi, Satoshi Sasaki, Kota Tateno, Atsushi Yokoo, Guoqiang Zhang, Sergent Sylvain, Akihiko Shinya
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Patent number: 12148752Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.Type: GrantFiled: July 26, 2022Date of Patent: November 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Han Lin, Wen-Tuo Huang, Yong-Shiuan Tsair
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Patent number: 12142602Abstract: A light emitting device including a first LED sub-unit having a thickness in a first direction, a second LED sub-unit disposed on a portion of the first LED sub-unit in the first direction, each of the first and second LED sub-units comprising a first-type semiconductor layer, a second-type semiconductor layer, and an active layer, a reflective electrode disposed adjacent to the first LED sub-unit and electrically connected to the first-type semiconductor layer of the first LED sub-unit, and a first ohmic electrode forming ohmic contact with the second-type semiconductor layer of the first LED sub-unit, in which the active layer of the first LED sub-unit is configured to generate light, includes AlxGa(1-x-y)InyP (0?x?1, 0?y?1), and overlaps the active layer of the second LED sub-unit in the first direction, and the active layer of the second LED sub-unit includes the same material as the active layer of the first LED sub-unit.Type: GrantFiled: June 20, 2022Date of Patent: November 12, 2024Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Hyeon Chae, Chang Yeon Kim, Ho Joon Lee, Seong Gyu Jang, Chung Hoon Lee, Dae Sung Cho
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Patent number: 12131980Abstract: A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.Type: GrantFiled: September 23, 2021Date of Patent: October 29, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toru Yamada, Takafumi Yamada
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Patent number: 12132016Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.Type: GrantFiled: August 8, 2023Date of Patent: October 29, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
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Patent number: 12119314Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.Type: GrantFiled: February 28, 2019Date of Patent: October 15, 2024Assignee: Mitsubishi Electric CorporationInventors: Nobuyoshi Kimoto, Tadatsugu Yamamoto
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Patent number: 12100696Abstract: A light emitting diode pixel for a display including a first LED sub-unit, a second LED sub-unit disposed on a portion of the first LED sub-unit, a third LED sub-unit disposed on a portion of the second LED sub-unit, and a reflective electrode disposed adjacent to the first LED sub-unit, in which each of the first to third LED sub-units comprises an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layers of the first, second, and third LED stacks is electrically connected to the reflective electrode, and the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit are configured to be independently driven.Type: GrantFiled: November 26, 2018Date of Patent: September 24, 2024Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Hyeon Chae, Chang Yeon Kim, Ho Joon Lee, Seong Gyu Jang, Chung Hoon Lee, Dae Sung Cho
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Patent number: 12087750Abstract: A stacked-substrate FPGA device is described in which a second substrate is stacked over a first substrate. Logic transistors (e.g., semiconductor devices and at least some conductive interconnections between them) are generally fabricated on (or over) a first substrate and memory transistors (e.g., SRAM cells and SRAM arrays) are generally fabricated on a second substrate over the first substrate. This has the effect of physically disposing elements of a CLB and a programmable switch on two different substrates. That is a first portion of a CLB and a programmable switch corresponding to logic transistors are on a first substrate and a second portion of these components of an FPGA corresponding to SRAM transistors is on a second substrate.Type: GrantFiled: September 25, 2018Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Willy Rachmady, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros
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Patent number: 12080726Abstract: A glossy display panel, a manufacturing method thereof and a display device are provided. The glossy display panel includes a display area and a non-display area; wherein the non-display area includes a binding area, and the glossy display panel includes a first conductive pattern located on a base substrate and located in the binding area; a first insulating layer covering the first conductive pattern, wherein the first insulating layer is provided with a first via hole, and an orthographic projection of the first via hole onto the base substrate is located within an orthographic projection of the first conductive pattern onto the base substrate; a glossy reflection layer, wherein an orthographic projection of the glossy reflection layer onto the base substrate does not overlap with an orthographic projection of the binding area onto the base substrate; and a chip on film.Type: GrantFiled: April 30, 2020Date of Patent: September 3, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xueyan Tian, Jianchao Zhu, Libin Liu, Liangjian Li, Caiyu Qu, Dengyun Chen, Ximeng Li
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Patent number: 12057419Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.Type: GrantFiled: July 26, 2022Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Fan Huang, Mao-Nan Wang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen