Abstract: The present technology relates to an image pickup device and electronic apparatus that enables suppression of dark current. There are included: a photoelectric conversion unit configured to perform a photoelectric conversion; a trench engraved in a semiconductor substrate; a negative fixed charge film having an oxide film, a nitrogen film, and an oxide film on a side wall of the trench; and an electrode film formed in the fixed charge film. The oxide film configuring the fixed charge film includes silicon monoxide (SiO), and the nitrogen film includes silicon nitride (SiN). The nitrogen film configuring the fixed charge film can also include a polysilicon film or a high dielectric constant film (high-k film). The present technology can be applied to, for example, a back-illuminated CMOS image sensor.

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer.

Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

Abstract: Methods and systems for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement may include a photonic chip comprising an input waveguide and a photodiode. The photodiode comprises an absorbing region with a p-doped region on a first side of the absorbing region and an n-doped region on a second side of the absorbing region. An optical signal is received in the absorbing region via the input waveguide, which is offset to one side of a center axis of the absorbing region; an electrical signal is generated based on the received optical signal. The first side of the absorbing region may be p-doped. P-doped and n-doped regions may alternate on the first and second sides of the absorbing region along the length of the photodiode. The absorbing region may comprise germanium, silicon, silicon/germanium, or similar material that absorbs light of a desired wavelength.

Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.

Abstract: A MEMS device having a body with a first and a second surface, a first portion and a second portion. The MEMS device further has a cavity extending in the body from the second surface; a deformable portion between the first surface and the cavity; and a piezoelectric actuator arranged on the first surface, on the deformable portion. The deformable portion has a first region with a first thickness and a second region with a second thickness greater than the first thickness. The second region is adjacent to the first region and to the first portion of the body.

Abstract: A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.

Abstract: The present disclosure is related to a display panel. The display panel may include a display substrate, a plurality of light emitting units on the display substrate, and a first organic layer covering the plurality of light emitting units. A surface of the first organic layer opposite from the light emitting units may include a plurality of raised portions and a plurality of recessed portions. The first organic layer may be directly in contact with the plurality of light emitting units.

Abstract: An integrated transformer includes a first and second inductors. The first inductor includes a first and second windings. The second inductor includes a third and fourth windings. The first, second, third and fourth windings have a first, second, third and fourth outer turn, respectively. At least one segment of the first (or second) outer turn substantially overlaps at least one segment of the third (or fourth) outer turn. The first and second outer turns are connected through a first segment and a first trace that cross each other, and the third and fourth outer turns are connected through a second trace and a second segment that cross each other. The first trace and the second segment are on the first metal layer, and the first segment and the second trace are on the second metal layer different from the first metal layer.

Abstract: Integrated circuit devices having optimized fin and gate dimensions are disclosed herein. An exemplary integrated circuit device includes a first multi-fin structure and a fourth multi-fin structure. A first gate structure traverses the first multi-fin structure, such that the first gate structure is disposed over a first channel region. A fourth gate structure traverses the fourth multi-fin structure, such that the fourth gate structure is disposed over a fourth channel region. The first gate structure includes a first gate dielectric having a first thickness, and the fourth gate structure includes a fourth gate dielectric having a fourth thickness. The first thickness is greater than the fourth thickness. The first multi-fin structure has a first pitch in the first channel region, and the fourth multi-fin structure has a fourth pitch in the fourth channel region. The first pitch is greater than the fourth pitch.

Abstract: The present invention provides a display panel, a manufacturing method of the display panel, and an intelligent terminal. The display panel has a photosensitive region for placing a photosensor of a camera. The display panel includes: an array substrate; and anodes disposed on the array substrate. The photosensitive region is arranged on one side of the array substrate away from the anodes, and the anode which is arranged corresponding to the photosensitive region has a patterned structure.

Abstract: An organic light emitting diode (OLED) display panel and an electronic device. The display panel includes a substrate and a transparent display area disposed on the substrate, the transparent display area comprises a plurality of pixel units and a plurality of transparent units disposed at intervals.

Abstract: Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate having pixel regions arranged in an array, each pixel region including a first sub-pixel region and a second sub-pixel region; a light emitting layer and a color conversion layer sequentially stacked on the base substrate; the color conversion layer includes a first color conversion block in at least the first sub-pixel region of at least one pixel region, each of the at least one first color conversion block includes at least two color conversion materials for converting a light component of a color into a light of a target display color, colors of the light components converted by the color conversion materials are different, the target display color is different from the color of the light emitted from the light emitting layer.

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.