Patents Examined by Nusrat Quddus
  • Patent number: 11736022
    Abstract: A power supply includes a primary winding, a secondary winding, a switch, and a controller. The secondary winding is magnetically coupled to the primary winding. The switch is coupled to the secondary winding and controls a state of current through the secondary winding. The controller controls the state of the switch based on an integrator voltage derived from monitoring a voltage from the secondary winding. For example, the controller activates the switch to an ON state in response to detecting a condition in which the magnitude of the monitored voltage of the secondary winding crosses a threshold value such as a magnitude of an output voltage produced from the secondary winding.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 22, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrey Malinin, Renato Bessegato, Yong Siang Teo
  • Patent number: 11736000
    Abstract: A power converter including a control circuit configured to output a control signal, and a semiconductor module. The semiconductor module includes a semiconductor chip, a switching device provided on the semiconductor chip, the switching device being configured to be turned on and off in response to the control signal, and a first temperature sensor configured to detect a temperature of the semiconductor chip. The control circuit is configured to monitor a thermal resistance of the semiconductor module based on a first temperature detected by the first temperature sensor, a second temperature corresponding to a temperature of the semiconductor module, and a power consumption of the switching device.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: August 22, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Haruhiko Nishio
  • Patent number: 11736016
    Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: August 22, 2023
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Seiichi Ozawa, Keisuke Kadowaki
  • Patent number: 11726511
    Abstract: According to one embodiment, a constant voltage circuit includes: a first gain stage that outputting a first voltage amplifying a difference voltage between a divided voltage of an output voltage and a reference voltage; a second gain stage outputting a second voltage amplifying the first voltage; a second transistor, one end of which is coupled to the input voltage terminal, and other end of which is coupled to an output voltage terminal, controlling the output voltage to be constant in accordance with the second voltage applied to the gate; and a first circuit selecting one of a first operation mode and a second operation mode. When the first operation mode is selected, a first current flows to the first node, and when the second operation mode is selected, a second current flows to the first node.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 15, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Akio Ogura
  • Patent number: 11720129
    Abstract: A voltage regulation system includes a voltage regulator configured to receive a first reference voltage and output a regulated voltage; a bias voltage generator comprising a diode-connect transistor configured to receive a bias current and output a reference gate voltage; and a plurality of switch-load circuits, each of said plurality of switch-load circuits comprising a common-drain transistor configured to receive power from the regulated voltage and control from the reference gate voltage via a switch controlled by a logical signal and output a supply voltage to load with a decoupling capacitor, wherein a size of the common-drain transistor is scaled from a size of the diode-connect transistor in accordance with a ratio between a current of the load and the bias current.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 8, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11720127
    Abstract: A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: SK hynix Inc.
    Inventor: Suk Hwan Choi
  • Patent number: 11711026
    Abstract: There is provided a power supply device configured to boost an input voltage to output an output voltage, the power supply device including: an oscillator circuit configured to receive the input voltage and to output an oscillation signal; a step-up circuit configured to output a boost voltage based on the oscillation signal; a first hysteresis comparator and a second hysteresis comparator configured to compare boost voltages with threshold values; a first switch that is connected between the oscillator circuit and the step-up circuit and that is controlled based on a comparison result of the first hysteresis comparator; and a second switch that is connected to an output terminal configured to output the output voltage and that is controlled based on a comparison result of the second hysteresis comparator.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 25, 2023
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Teppei Hayashi
  • Patent number: 11709513
    Abstract: One or more embodiments relate to a multi-phase voltage regulator with AVP or droop configured to implement a non-linear load line. According to certain aspects, the non-linear load line can have a non-linear or zero slope in a first current/voltage region and a constant non-zero slope in second current/voltage region. In embodiments, the non-linear or zero slope region can specify that for any value of output current in that region, the output voltage will be the same predetermined value. The non-zero slope region can specify that for any value of the output current in that region, output current will be multiplied by a constant non-zero droop resistance value.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: July 25, 2023
    Assignee: Renesas Electronics America Inc.
    Inventors: Travis Guthrie, Jim Toker, Shea Petricek
  • Patent number: 11711025
    Abstract: A power semiconductor module includes at least one upper arm provided between a positive electrode line and a node and including a power semiconductor device and a freewheeling diode connected in parallel, at least one lower arm provided between a negative electrode line and the node and including a power semiconductor device and a freewheeling diode connected in parallel, and a snubber circuit provided between the positive electrode line and the negative electrode line. The snubber circuit includes a snubber capacitor and a snubber resistor connected in series. At least one control terminal outputs a voltage representing the temperature of the snubber resistor or a voltage related to the temperature of the snubber resistor to a driver that drives the power semiconductor device.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 25, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Horiguchi, Takayoshi Miki
  • Patent number: 11703897
    Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 18, 2023
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
  • Patent number: 11695327
    Abstract: Embodiments of a power converter are disclosed. In an embodiment, the power converter comprises a power factor correction (PFC) stage circuit, an emulation circuit and a controller. The PFC stage circuit is configured to produce an output signal on an output terminal. The PFC stage circuit includes an inductor coupled between a rectifier and the output terminal and a switch coupled to the inductor. The emulation circuit is connected to the PFC stage circuit to generate an emulated current that corresponds to current through the inductor of the PFC stage circuit. The emulated current is generated based on a voltage signal at a node between the inductor and the output terminal and a sensed current at a sense resistor connected to the rectifier. The controller is connected to the emulation circuit to receive the emulated current and generate a control signal for the switch of the PFC stage circuit based on the emulated current.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 4, 2023
    Assignee: NXP B.V.
    Inventors: Hans Halberstadt, Alfred Grakist
  • Patent number: 11695345
    Abstract: Disclosed herein is an improved flyback converter that separates the magnetic components of the converter into a transformer and a separate, discrete energy storage inductor. This arrangement can improve the operating efficiency of the converter by reducing the commutation losses as compared to a conventional flyback converter. The magnetic components may be constructed on separate magnetic cores or may be constructed on magnetic cores having at least one common element, thereby allowing for at least partial magnetic flux cancellation in a portion of the core, reducing core losses.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: July 4, 2023
    Assignee: Apple Inc.
    Inventors: Vijay G. Phadke, Prudhvi Mohan Maddineni
  • Patent number: 11687104
    Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: June 27, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kuan Chuang Koay, Hua Guan, Jize Jiang
  • Patent number: 11682972
    Abstract: Controller circuitry can employ a method to provide control signals to bridge switches operating an inductor for switched-mode inductive buck-boost voltage regulation. The buck mode can operate the bridge switches in a buck current control mode when the input voltage exceeds the output voltage. The boost mode can operate the bridge switches in a boost current control mode when the output voltage exceeds the input voltage. The buck-boost transition mode can operate the bridge switches in a peak buck-boost current control mode that minimizes a minimum duty cycle (having a minimum “on” duty time and a minimum “off” duty time) when the output voltage is approximately equal to the input voltage during a transition from at least one of the current control buck mode to the current control boost mode or from the current control boost mode to the current control buck mode.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 20, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Min Kyu Song, Min Chen
  • Patent number: 11664659
    Abstract: A polarity reversal protection arrangement having a transistor circuit, an amplifier circuit and an output driver stage, wherein the amplifier circuit is connected to the output driver stage and the output driver stage is connected to the transistor circuit and the transistor circuit is arranged between a first connection node and a second connection node of the polarity reversal protection arrangement, such that an electrical connection between the first connection node and the second connection node is able to be created or disconnected by way of the transistor circuit, wherein the output driver stage is designed as a tri-state stage. A method for operating the polarity reversal protection arrangement and to a corresponding use.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: May 30, 2023
    Assignee: Continental Teves AG & Co. OHG
    Inventor: Thorsten Fahlbusch
  • Patent number: 11664741
    Abstract: A power-control device comprises an energy-import portion and an energy-export portion. The power-control device may additionally include a general processing and power supply circuit providing linear control of the power-control device's production of power to the load. The energy-import portion is coupled between a VLINE terminal and a load terminal, and is capable of importing energy to the load terminal during a first portion and a third portion of an alternating voltage VAC waveform. The energy-export portion is coupled between the load terminal and a NEU terminal, and is capable of exporting energy from the load terminal during a second portion and a fourth portion of the alternating voltage VAC waveform. The first, second, third and fourth portions of the alternating voltage VAC waveform are equal to a period of the alternating voltage VAC waveform and respectively are consecutive during the period of the alternating voltage VAC waveform.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 30, 2023
    Inventor: Susan Rhodes
  • Patent number: 11664732
    Abstract: This present invention is an invented synchronous clock generator for the multiphase DC-DC converter system, comprising a front-end buffer circuit, a ramp signal generator circuit, a configurable equally divided reference voltage generator circuit, a set of comparators, a 10-ns pulse generator, multiple 30-ns pulse generators, and a pulse combination circuit. The synchronous clock generator can produce a clock pulse signal SYNC at N (total phase number) times the single-phase switching frequency. Within one synchronous loop period, a 10-ns pulse is first generated and followed by N-1 30-ns pulses. The master power stage chip detects the 10-ns pulse, and all the slave power stages detect and count the 30-ns pulses to determine when to set their output signal PWM. Thus, the invention can produce the new SYNC signal immediately with balanced phase shift while allowing the changing of the total phase number N by the total phase number register.
    Type: Grant
    Filed: June 5, 2021
    Date of Patent: May 30, 2023
    Inventor: Guanghua Ye
  • Patent number: 11656643
    Abstract: A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 23, 2023
    Assignee: NXP USA, Inc.
    Inventors: Siamak Delshadpour, Xueyang Geng
  • Patent number: 11652410
    Abstract: Systems and methods are provided for regulating a power converter. An example system controller includes: a driver configured to output a drive signal to a switch to affect a current flowing through an inductive winding of a power converter, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. One minus the duty cycle is equal to a parameter. The system controller is configured to keep a multiplication product of the duty cycle, the parameter and the duration of the on-time period approximately constant.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 16, 2023
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Qian Fang, Cong Lan, Lieyi Fang
  • Patent number: 11625054
    Abstract: A voltage-to-current converter includes a first transistor having a drain coupled to a first node, a second transistor having a drain coupled to the first node, an operational amplifier having a first input terminal configured to receive a reference voltage and a second input terminal coupled to a source of the first transistor or a source of the second transistor, a control circuit having an input terminal coupled to an output terminal of the operational amplifier, a first output terminal coupled to a gate of the first transistor, and a second output terminal coupled to a gate of the second transistor, a first resistor coupled between the source of the first transistor and a ground, and a second resistor coupled between the source of the second transistor and the ground. An output current of the voltage-to-current converter is generated from the first node.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: April 11, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Hsiang-Yi Chiu