Abstract: The field effect transistor includes a control terminal (G), a first main terminal (S) and a second main terminal (D1). The control terminal (G) is included to be coupled to gate voltage means which are adapted to provide a control voltage (Vg) which controls a flow of carriers (e) flowing from the first main terminal (S) to the second main terminal (D1). The field effect transistor further includes a third main terminal (D2) which is positioned and adapted in order to enable a high input resistance control current means (CS), which is coupled to the third main terminal (D2), to deviate part (e′) of the flow of carriers from the first main terminal (S) to the third main terminal (D2). The third main terminal is called the double drain (D2) of the field effect transistor.
Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.
Abstract: In encapsulating an optocomponent a leadframe (51) is used for the electrical connection of the component, the leadframe having a flag (53), to which the main body of the optocomponent is attached. The flag (53) is located asymmetrically at an outer edge of the leadframe and is, in the encapsulating operation, placed close to a sidewall in a mould cavity in a mould. Thereby an optical interface of standard type can be obtained in the wall of the capsule. Further, the flag (53) is flexibly attached, by means of zigzag-shaped bridges (67), to other portions of the leadframe so that the flag and thus the optocomponent will have a possibility to be resiliently and flexibly displaced a little at the positioning thereof in the mould cavity in the mould in relation to the other portions of the leadframe, in particular to its outer frame portions (61) and bridge portions (59).
Abstract: A new method for fabricating a storage capacitor, on a dynamic random access memory (DRAM) cell, having a ring-type sidewall was accomplished. The method involves opening the self-aligned node contact to the source/drain area of the field effect transistor and forming the bottom capacitor electrode. The same photoresist mask used to open the self-aligned node contact is later used to mask and partially etch the polysilicon bottom capacitor electrode to form the ring-type sidewall on the bottom electrode. The storage capacitor is then completed by forming a thin capacitor dielectric and depositing the top electrode. The method provides a simple process that increases the capacitance of the storage capacitor by about 40 percent while not adversely affecting the leakage current.
July 13, 1994
Date of Patent:
July 4, 1995
Industrial Technology Research Institute
Daniel Hao-Tien Lee, Chao-Ming Koh, Yu-Hua Lee
Abstract: A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).
February 8, 1993
Date of Patent:
July 19, 1994
Gregory L. Westbrook, William M. Williams
Abstract: A method for in-situ doping of deposited silicon is disclosed. The method utilizes low temperature of approximately 560.degree. C., low pressure of approximately 300 mTorr, and low phosphine to silane ratio of approximately 0.0008 to form phosphorus doped silicon. The method is manufacturable in an automated LPCVD reactor. It allows relatively uniform defect free silicon films of low resistivity and good conformality and step coverage to be deposited at sufficient deposition rates over large semiconductor wafer lots for high wafer throughput.
Abstract: To manufacture a semiconductor device, a buried layer, epitaxial layer and an element separating layer are formed on a substrate, in order; a first resist film is formed thereon and an opening at which a first base is to be formed in patterned in the epitaxial layer; a first base is formed by ion-injection with the first resist film as a mask; the first resist film is removed and an interlayer insulating film is formed; a second resist film is formed thereon and an opening at which a second base is to be formed is removed by etching; the bottom surface of the opening portion is oxidized to form a second base under the same opening due to reduction of impurity concentration; the oxide film is removed and a polysilicon film is formed; an emitter electrode is patterned; and an emitter layer is formed on the second base by ion injection and thermal diffusion. Since the first and second base can be formed in self-alignment condition, the element can be minimized without providing a mask matching margin.
Abstract: Metal boride powders can be produced with a predetermined particle size by controlling reaction conditions. The metal boride powder is produced by reacting a solid boron source, a metal source and a reductant under conditions sufficient to produce a metal boride powder with a particle size correlating to that of the solid boron source. The reaction is preferably stopped after the formation of products but before any appreciable crystal growth occurs.
Abstract: A method is set forth comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer, with the object of creating gate islands which extend in the direction of highly doped parts (22b, 23b) of source and drain zones. According to the invention, the gate islands (15) the first delimited in the first polycrystalline layer (12), after which the edges of these islands are protected with provisional spacers (20a) of an oxidation-preventing material, so that after ion implantation of the weakly doped portions (22, 23) of the source and drain, non-protected parts of the device can be re-oxidized. After this, the provisional spacers (20a) are removed and the second polycrystalline layer (30) is deposited, thus achieving electrical contact with the previously protected edges of the islands (15) of the first polycrystalline layer (12). Widened gate islands are finally formed by the insulating spacer technique (32).
Abstract: Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.
Abstract: The present invention relates to compositions and methods for inhibiting nonenzymatic cross-linking (protein aging). Accordingly, a composition is disclosed which comprises an agent capable of inhibiting the formation of advanced glycosylation endproducts of target proteins by reacting with the carbonyl moiety of the early glycosylation product of such target proteins formed by their initial glycosylation. Suitable agents contain an active nitrogen-containing group, such as a hydrazine group. Particular agents comprise aminoguanidine derivatives. The method comprises contacting the target protein with the composition. Both industrial and therapeutic applications for the invention are envisioned, as food spoilage and animal protein aging can be treated.
Abstract: In place of the conventional silicon source materials used in the prior art method for the preparation of silicon carbide whiskers, the inventive method utilizes a hydrolysis product of a chlorosilane compound R.sub.a SiCl.sub.4-a or a chlorodisilane compound R.sub.b Si.sub.2 Cl.sub.6-b, in which R is a hydrogen atom or a monovalent hydrocarbon group, a is zero to 3 and b is 1 to 5, as the silicon source which is intimately mixed with a powder of carbon and the mixture is heated at 1400.degree. to 1700.degree. C. to give silicon carbide whiskers in a high conversion. Alternatively, the hydrolysis of the chloro(di)silane compound is performed in an aqueous medium in which a powder of carbon is dispersed in advance so that the hydrolysis product as formed is already a mixture with the carbon powder.
Abstract: A lubricating composition of about 90 to about 99% by weight of a lubricant and about 1 to about 5% by weight of an organometallic phthalocynaine, preferably a polymeric organometallic phthalocyanine complex, including nitrogen-substituted analogues thereof, where the complexed metal ion is preferably a Group IVA metal and provides increased time of machine operation to failure by improving oil lubricated bearing performance. Phthalocynanine peripheral ring substituents and attached to the phthalocyanine increase solubility in aqueous and organic lubricants.
Abstract: Composition containing one or more lubricants or hydraulic oils based on mineral oil, synthetic oils or mixtures thereof and at least one compound of the formulae I, II or III, ##STR1## in which R.sup.1, R.sup.2, R.sup.3, R.sup.4 R.sup.5 and R.sup.6 independently of one another are C.sub.1 -C.sub.24 alkyl or C.sub.1 -C.sub.24 alkyl which can be substituted by oxo or thio groups, or C.sub.3 -C.sub.24 alkyl which can be interrupted by ##STR2## --S-- and/or --N(R.sup.8)-- in which R.sup.8 is hydrogen or C.sub.1 -C.sub.12 alkyl and which can be substituted by oxo or thionogroups, or C.sub.2 -C.sub.24 alkenyl or phenyl or naphthyl which is unsubstituted or substituted by one or two C.sub.1 -C.sub.12 alkyl, C.sub.2 -C.sub.24 carboalkoxy or nitro groups; or are C.sub.7 -C.sub.10 phenylalkyl, and R.sup.1, R.sup.2, R.sup.3 and R.sup.4 additionally are hydrogen, or R.sup.1 and R.sup.2, or R.sup.1 and R.sup.
Abstract: A silicon-on-insulator substrate having a very low threading dislocation density is made by implanting oxygen ions into a silicon substrate while heating the substrate to form a layer of silicon dioxide buried in the silicon substrate and annealing the implanted substrate at high temperature in a novel furnace incorporating a polysilicon tube to constrain the annealing temperature to be uniform over the entire substrate. The silicon-on-insulator substrate is particularly useful for the manufacture of semiconductor devices formed in thin silicon films.
Abstract: A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.
Abstract: A method of manufacturing an EPROM IC device encapsulated in a plastic-molded package having a window for passing ultraviolet rays therethrough. An EPROM IC chip is fixed to a chip mounting region of a lead frame. The EPROM IC chip is placed in a hollow container made of a material capable of passing ultraviolet rays therethrough. A resin material capable of passing ultraviolet rays therethrough is introduced into the hollow container. A resultant structure is encapsulated plastic material except a surface of the hollow container, above the EPROM IC chip.
Abstract: An electrolytic capacitor having very thin spacer layers is produced by a process in which at least two of the surfaces of an anode valve action metal foil and a cathode metal foil are coated with a photosensitive polymer resin solution; the resultant photosensitive polymer resin solution layers are solidified; the solidified photosensitive polymer resin coatings are masked with a negative or positive masking film having a desired pattern and irradiated with an actinic radiation to partly harden the photosensitive polymer resin coatings in accordance with the masking pattern; after removing the masking film, the irradiated photosensitive polymer resin coatings are developed with a developing liquid to provide spacer layers consisting of hardened portions of the photosensitive polymer resin coatings; the anode and cathode metal foils having the spacer layers are superposed on each other in such a manner that at least one spacer layer is located between the superposed anode and cathode metal foils and at least
January 22, 1986
Date of Patent:
August 16, 1988
Ube Industries Ltd., Marcon Electronics Corp. Ltd., High Man Parts Corp. Ltd.
Abstract: The fabrication of a two-phase buried channel silicon CCD involves the use of arsenic diffusion out of selected regions of an overlying oxide layer into selected portions of a buried channel in the underlying silicon intended to serve as the storage region of the first phase set of polysilicon gate electrodes. To eliminate various problems, the oxide layer into which the arsenic is implanted for later outdiffusion is grown in a wet oxidizing ambient, and the arsenic implantation is followed with a restore oxide anneal step involving heating at a moderate temperature before the later outdiffusion by heating at a high temperature. Additionally, an oxide layer intended to serve as the gate oxide underlying a second-phase set of polysilicon gate electrodes is formed by heating the wafer in a dry oxidizing ambient.
Abstract: Process for the production of a monolithic integrated optical device incorporating a semiconductor laser and an optical waveguide, as well as to a device obtained by this process.The substrate is given a profile having at least one step. On said substrate is deposited by a single epitaxy operation performed in the vapour phase and in a successive manner a first confinement layer, a guidance layer made from a material transparent for the radiation emitted by the laser, a second confinement layer, an active layer, a third confinement layer and a contact layer. The transparent material has a refractive index higher than the indices of the confinement layers surrounding the same. Thickness values are given to the different layers such that the active layer of the lower stack faces the transparent layer of the upper stack.Application to optical telecommunications.
November 13, 1985
Date of Patent:
January 19, 1988
Louis Menigaux, Alain Carenco, Pierre Sansonetti