Patents Examined by Olik Chaudhuri
  • Patent number: 10079214
    Abstract: A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower side; a first and second electrode, and a housing, wherein the power semiconductor element is arranged between the first and second electrode such, that the upper side comprises a first contact portion being in contact with the first electrode and a first free portion not being in contact with the first electrode, and wherein the lower side at least comprises a second contact portion being in contact with the second electrode, and wherein a channel is provided fluidly connecting at least a part of the first free portion with a predetermined degassing point of the housing for guiding an overpressure, which overpressure results from plasma and/or gas occurring in a failure mode, from the first free portion to the predetermined degassing point.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 18, 2018
    Assignee: ABB Schweiz AG
    Inventors: Jaroslav Homola, Ladislav Dort, Ladislav Radvan
  • Patent number: 10044170
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 7, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10038015
    Abstract: An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 31, 2018
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Tianyi Wu, Jun Ma
  • Patent number: 10020355
    Abstract: A photosensor includes a first light-shielding layer provided on an insulating surface; a first insulating layer covering the first light-shielding layer; a semiconductor layer provided on the first insulating layer, the semiconductor layer being connected to a first electrode and a second electrode, and the semiconductor layer configuring a diode; a second insulating layer covering the semiconductor layer; an opening provided in the second insulating layer so as to surround the semiconductor layer as viewed from a planar direction and the opening reaching at least the first insulating layer; and a second light-shielding layer covering at least a side wall of the opening.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 10, 2018
    Assignee: Japan Display Inc.
    Inventor: Ryoichi Ito
  • Patent number: 10014294
    Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 3, 2018
    Assignee: ABLIC Inc.
    Inventors: Hirofumi Harada, Masayuki Hashitani
  • Patent number: 9941191
    Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chiahsun Tseng, Jin Liu, Lei Zhuang
  • Patent number: 9893227
    Abstract: A photodiode for detecting photons comprising a substrate; first semiconducting region suitable for forming a contact thereon; a first contact; a second semiconducting region comprising an absorption region for the photons and being formed of a semiconductor having one or more of a high surface recombination velocity or a high interface recombination velocity; a second contact operatively associated with the second region; the first semiconducting region and the second semiconducting region forming a first interface; the second semiconducting region being configured such that reverse biasing the photodiode between the first and second contacts results in the absorption region having a portion depleted of electrical carriers and an undepleted portion at the reverse bias point of operation; the undepleted portion being smaller than the absorption depth for photons; whereby the depletion results in the creation of an electric field and photogenerated carriers are collected by drift; and a method of making.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 13, 2018
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Anand Venktesh Sampath, Michael Wraback, Paul Shen
  • Patent number: 9892910
    Abstract: A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Juntao Li
  • Patent number: 9882159
    Abstract: The invention relates to a voltage-light conversion device (1) like an OLED comprising a structured electrically conducting layer (3) on a substrate (2) and a further layer (60) that is part of an encapsulation and which comprises a layer edge (63). The electrically conducting layer comprises in an edge region (70) close to the layer edge a structure edge (10), wherein at least a part of the structure edge is not perpendicular to the layer edge. Since in the edge region at least a part of the structure edge is not perpendicular to the layer edge, during the production process for producing the further layer a possible flow of initially liquid layer material along the structure edge can be directed such that the liquid material remains relatively close to the desired layer edge, i.e. the liquid material can be better locally confined.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: January 30, 2018
    Assignee: OLEDWORKS GMBH
    Inventors: Soren Hartmann, Meik Rekittke, Pieter Gijsbertus Maria Kruijt
  • Patent number: 9882016
    Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
  • Patent number: 9859351
    Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate and a plurality of pixels formed over the substrate, each pixel including a first region from which light is emitted and a second region through which external light is transmitted. The display also includes a plurality of pixel circuit units each formed in the first region and including at least one thin-film transistor, an inorganic insulating film formed in the second region, a transparent conductive film formed over at least a portion of the inorganic insulating film, and an organic insulating film covering the pixel circuit units and at least a portion of the transparent conductive film. The display further includes a plurality of first electrodes formed over the organic insulating film and in the first regions of the pixels.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 2, 2018
    Assignee: Sansung Display Co., Ltd.
    Inventors: Sangho Moon, Sungho Kim, Sangkyung Lee
  • Patent number: 9853043
    Abstract: A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-st
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 26, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Daxin Mao, Tong Zhang, Johann Alsmeier, Wenguang Shi, Henry Chien
  • Patent number: 9837338
    Abstract: A terminal case formed by integrally molding a lead frame and a case that has internally an inner face on which the lead frame is mounted and has externally a step portion fixed to a circuit block having an insulating substrate and semiconductor chips formed on the insulating substrate. An opening portion is formed between the step portion and the inner face so as to extend through them, and the opening portion is filled with an adhesive to bond the insulating substrate to the step portion. Since a connecting area to which a bonding wire of the lead frame is ultrasonically bonded is fixed, it is possible to reduce the bonding failures of the lead frames.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 5, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tadahiko Sato
  • Patent number: 9831271
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 28, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Patent number: 9831328
    Abstract: Some embodiments are directed to a bipolar junction transistor (BJT) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The BJT includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions. The base region is arranged within, and in contact with, a conductive base layer, which delivers current to the base region. The base region includes a planar bottom surface, which increases contact area between the base region and the semiconductor substrate, thus decreasing resistance at the collector/base junction, over some conventional approaches. The base region can also include substantially vertical sidewalls, which increases contact area between the base region and the conductive base layer, thus improving current delivery to the base region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lih-Tien Shyu, Yeur-Luen Tu
  • Patent number: 9824923
    Abstract: A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: November 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dzafir Shariff, Kwong Loon Yam, Lai Yee Chia, Yung Kuan Hsiao
  • Patent number: 9825048
    Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 21, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Raul Adrian Cernea
  • Patent number: 9824948
    Abstract: A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 21, 2017
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Erick Merle Spory
  • Patent number: 9825027
    Abstract: A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side by side between the first trenches. A second electrode is formed in each of the two second trenches. A first impurity region is formed between the first trench and the second trench; a second impurity region is formed to abut on the first trench; a third impurity region is formed to abut on the second trench; a fourth impurity region, which is formed between two of the second trenches and has a higher impurity concentration than the first impurity region; and a fifth impurity region is formed below the first impurity region and the fourth impurity region. A third electrode is formed to be electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: November 21, 2017
    Assignee: Sanken Electric Co., LTD.
    Inventors: Shunsuke Fukunaga, Taro Kondo
  • Patent number: 9818742
    Abstract: An isolation structure prevents inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate. The first and second semiconductor devices each include a gate region and at least one active region. A first channel stop region is configured to surround the first semiconductor device. A second channel stop region is configured to surround the second semiconductor device. A first field plate is located above at least part of the first channel stop region, and overlaps the gate region of the first semiconductor device in a first overlap region. A second field plate is located above at least part of the second channel stop region, and overlaps the gate region of the second semiconductor device in a second overlap region.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: November 14, 2017
    Assignee: POLAR SEMICONDUCTOR, LLC
    Inventor: William Larson