Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a carrier holding unit and is arranged on one side of the rectangle of the photodiode region as a region having a side longer than the one side. In a MOS unit region, an output unit region including an output unit having a side longer than the other side which crosses the one side of the rectangle of the photodiode region is arranged on the other side. A gate region and the FD region are arranged between the photodiode region and the capacitor region.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at least partially inhibit irradiation of the radiation sensitive component. The radiation sensitive component can be doped silicon, chalcogenide, polymeric random access memory, or any other component that is altered when irradiated with one or more specific frequencies of radiation. The curable component can be an adhesive, an underfill layer, an encapsulant, a stand-off, or any other feature constructed of a material that requires curing by irradiation.

Abstract: Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate.

Abstract: A method may be provided for preparing a semiconductor light-emitting device. The method may include: preparing a first wafer in which a semiconductor multi-layered light-emitting structure is disposed on an upper part of an initial substrate; preparing a second wafer which is a supporting substrate; bonding the second wafer on an upper part of the first wafer; separating the initial substrate of the first wafer from a result of the bonding; and fabricating a single-chip by severing a result of the passivation. Other embodiments may be provided.

Abstract: A method of packaging a power light emitting diode (LED). The method may include providing a printed circuit board (PCB) wherein first and second copper (Cu) thin films are formed on both faces of the PCB respectively, forming a single upper opening through an entire thickness of the first Cu thin film and an partial thickness of the PCB, forming a plurality of lower openings, each lower opening extending vertically from the upper opening to the second Cu thin film, forming solder pads on the first Cu thin film, filing a cream solder in the upper opening and the plurality of lower openings so as to be in-plane with the solder pads, mounting a power LED on the PCB so that lead frames of the LED are aligned with the solder pads and a heat-discharge region of the LED is aligned with the cream solder, and soldering the cream solder.

Abstract: A method for manufacturing an LED package includes following steps: providing a base with an LED chip mounted on the base; providing a porous carrier with a plurality of holes, and disposing the base on the porous carrier; providing a film with a phosphor layer attached on the film; providing a mold, and putting the porous carrier, the base, the LED chip, and the film into the mold; extracting air from the mold to an external environment through the holes of the porous carrier, and/or, blowing air toward the film to urge the film to move toward the LED chip, resulting in that the film is conformably attached onto the LED chip and the base; and solidifying the phosphor layer on the LED chip by means of heating whereby the phosphor is conformably and securely attached on the LED chip.

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.

Abstract: An LED device is disclosed in which an LED chip is encapsulated in a encapsulant. The LED device includes an LED chip mounted on a support and electrically connected and an encapsulant encapsulating the LED chip, wherein the encapsulant is a transparent amorphous solid made of a metal oxide, and the solid contains as a major component at least one metal oxide selected from the group consisting of Al2O3, MgO, ZrO, La2O3, CeO, Y2O3, Eu2O3, and ScO.

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.

Abstract: A submount for a semiconductor light emitting device includes a semiconductor substrate having a cavity therein configured to receive the light emitting device. A first bond pad is positioned in the cavity to couple to a first node of a light emitting device received in the cavity. A second bond pad is positioned in the cavity to couple to a second node of a light emitting device positioned therein. Light emitting devices including a solid wavelength conversion member and methods for forming the same are also provided.

Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region.

Abstract: A process is provided for producing a doped organic semiconductive layer, comprising the process steps of A) providing a matrix material, B) providing a dopant complex, and C) simultaneously applying the matrix material and the dopant complex to a substrate by vapor deposition, wherein, in process step C), the dopant complex is decomposed and the pure dopant is intercalated into the matrix material.

Abstract: A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.

Abstract: A light-emitting device and method for manufacturing the same are described. A method for manufacturing a light-emitting device comprising steps of: providing a growth substrate, wherein the growth substrate has a first surface and a second surface; forming a light-absorbable layer on the first surface of the growth substrate; forming an illuminant epitaxial structure on the light absorbable layer; providing a laser beam and irradiating the second surface of the growth substrate, wherein the laser beam wavelength is greater than 1000 nm; and removing the growth substrate.

Abstract: A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element.

Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.