Patents Examined by Olivia T. Luk
  • Patent number: 7101721
    Abstract: An adaptive manufacturing process for a Film Bulk Acoustic Resonator (FBAR) tests the FBAR circuit during manufacturing to determine a resonant frequency thereof. Reactive tuning elements may be adjusted as needed depending on the testing to change the resonant frequency to a desired resonant frequency. In an exemplary embodiment, predetermined masks may be applied to modify the tuning elements.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 5, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Jon D. Jorgenson, David Dening, Victor Steel
  • Patent number: 6998349
    Abstract: A system and method of generating RF includes a supply voltage source, an oscillator, an output amplifier, a load network, a peak voltage detector and a comparator circuit. The oscillator has a control signal input and an RF signal output. The output amplifier is coupled to the oscillator output. The load network is coupled between an output of the output amplifier and an output of the RF generator. The peak voltage detector is coupled across the output amplifier. The comparator circuit includes a first input coupled to the supply voltage source, a second input coupled to an output of the peak voltage detector, and a comparator output coupled to the oscillator control signal input.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: February 14, 2006
    Assignee: Lam Research Corporation
    Inventors: Thomas W. Anderson, Andras Kuthi
  • Patent number: 6949471
    Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: September 27, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chen Hao, Hung-Jen Lin, Min-Hwa Chi, Chih-Heng Shen
  • Patent number: 6949465
    Abstract: According to this invention, residues generated after selectively removing a low-dielectric-constant film such as SiOC can be effectively removed without damage on an insulating film or metal film. Specifically, residues 126 and 128 generated after forming an interconnect trench in an SiOC film 116 are removed using a fluoride-free weak alkaline amine stripper. After the removing step, the wafer is rinsed with isopropyl alcohol and then dried without drying with pure water.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: September 27, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Kenichi Tokioka, Yoshiko Kasama, Tatsuya Koito, Keiji Hirano
  • Patent number: 6943055
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6936496
    Abstract: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through the junction oxide. A circuit is also provided, having first and second close proximity conductors, and a nanowire filament fused between the close proximity conductors.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 30, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Neal W. Meyer, James E. Ellenson
  • Patent number: 6933233
    Abstract: A liquid material supply system in which an inert gas is injected into a material tank accommodating a liquid material so as to discharge the liquid material into a liquid material discharge pipe connected to the material tank and that the inert gas dissolved or mixed in the discharged liquid material is trapped by a gas trap provided on the liquid material discharge pipe, is constructed in such a manner that when a dissolution temperature characteristic of the inert gas with respect to the liquid material is negative, an upstream side of the liquid material discharge pipe with respect to the gas trap is heated while the downstream side of the liquid material discharge pipe with respect to the gas trap is cooled.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 23, 2005
    Assignee: Stec, Inc.
    Inventors: Makoto Yonebayashi, Hideaki Miyamoto, Tetsuo Shimizu
  • Patent number: 6933177
    Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: August 23, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: John P. Tellkamp
  • Patent number: 6933240
    Abstract: A hard mask made from polysilicon is used to etch a layer to be patterned. The hard mask is patterned using a resist mask. The etching of the hard mask is carried out in such a way that the openings which are etched into the hard mask have inclined sidewalls. This reduces the cross section of the openings, with the result that smaller openings can be formed in the layer that is to be patterned than the openings which have been predetermined by the resist mask. The hard mask is etched using only HBr. The inclination of the openings etched into the hard mask can be set by way of the TCP power and/or the bias power of a TCP etching chamber, and/or by way of the HBr flow rate.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: August 23, 2005
    Assignee: Infineon Technologies AG
    Inventors: Laura Lazar, Matthias Kronke
  • Patent number: 6919281
    Abstract: In a method of manufacturing a semiconductor device, a flexible tube connects at least part of a path extending from a reaction chamber to a detoxification device through a vacuum pump. The flexible tube has a tube body made of hard material, the tube body having projected parts and depressed parts and a cover provided over an outer surface of the tube body, the cover being made of elastic material, the cover being in contact with around the projected parts of the tube body and formed over the depressed parts of the tube body so that a vacant space is formed between the tube body and the cover. Then, a semiconductor substrate is disposed within the reaction chamber. The vacuum pump is activated to bring the reaction chamber into a pressure-reduced state. A reaction gas is supplied to the reaction chamber. Finally, the reaction gas causes to react to thereby deposit a reactant on the semiconductor substrate.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: July 19, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Eiji Takaara
  • Patent number: 6919215
    Abstract: The present invention provides a manufacturing method of a light emitting device in which the number of display panels manufactured from one substrate is increased and display panel is mass produced is provided. One feature of the invention is that the shipping is performed not by separating the substrate over which a plurality of light emitting regions is formed and attaching the FPC to the each piece thereof but before separating, namely in the incomplete state (that can be also referred to as semi end products). However, the invention has a structure in which the inspection can be partly carried out before the shipping.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: July 19, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakazu Murakami
  • Patent number: 6916749
    Abstract: A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: July 12, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kouichirou Tsujita, Akihiro Nakae
  • Patent number: 6914011
    Abstract: A film deposition system comprises a chamber having an internal space, a support part provided in the internal space of the chamber for supporting a substrate, a gas supply part supplying gas to the internal space and a heating part heating the substrate. After an oxide film is formed on the substrate, the gas supply part supplies oxygen or a gas mixture of oxygen and ozone to the internal space while the heating part heats the substrate. Thus provided is a film deposition system capable of flattening an oxide film.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: July 5, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshio Hayashide, Kazuo Kobayashi, Yasufumi Morimoto
  • Patent number: 6905978
    Abstract: A method of forming an interlayer insulation film on a semiconductor substrate using plasma CVD includes introducing a source gas into a reaction chamber, applying radio-frequency power after the source gas is brought in, introducing an oxidizing gas with or without an additive gas into the reaction chamber after the completion of supplying the source gas and applying the radio-frequency power, and applying the radio-frequency power again. The concentration of the oxidizing gas may be 0.3% or higher and a processing time period by the oxidizing gas may be three seconds or longer.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 14, 2005
    Assignee: ASM Japan K.K.
    Inventors: Naoto Tsuji, Yukihiro Mori, Satoshi Takahashi, Ryo Kawaguchi
  • Patent number: 6903028
    Abstract: The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer. As the etch rate is higher for the highly doped oxide than that for the lightly doped oxide, high selectivity of etching between such layers can therefore be attained. A lightly doped silicon oxide layer may therefore be used to stop etching at an optimal thickness over the complicated layer of substrate. The lightly doped silicon oxide area may be covered with a layer of highly doped silicon oxide layer which may be etched with a specific etchant.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: June 7, 2005
    Assignee: 1st Silicon (malaysia) Sdn Bhd
    Inventor: Jung Woo Young
  • Patent number: 6897076
    Abstract: A lithography system includes a pre-process apparatus which performs a pre-process for a substrate and an exposure apparatus which exposes the substrate pre-processed by the pre-process apparatus to a pattern. The pre-process apparatus includes a first control unit which transmits an instruction for starting exposure preparation to the exposure apparatus, and the exposure apparatus includes a second control unit which causes exposure preparation to start in accordance with the instruction transmitted from the pre-process apparatus.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 24, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoshi Sugiura
  • Patent number: 6878559
    Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: April 12, 2005
    Assignees: Applied Materials, Inc., Advanced Micro Devices, Inc.
    Inventors: Peter G. Borden, G. Jonathan Kluth, Eric Paton
  • Patent number: 6849559
    Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: February 1, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Vaidyanathan Balasubramaniam, Yasunori Hatamura, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
  • Patent number: 6841489
    Abstract: A semiconductor device manufacturing method includes the steps of (a) introducing a first substrate into a first CVD chamber; (b) raising the first substrate temperature to a predetermined value; (c) growing a film on the first substrate by supplying vapor phase material in a material line to the first chamber; (d) introducing a second substrate into a second CVD chamber; (e) raising the second substrate temperature to the predetermined value; and (f) growing a film on the second substrate by supplying the vapor phase material to the second chamber. Steps (c) and (f) supply the vapor phase material selectively to the first and second chambers, respectively. In step (f) after step (c), the chamber to which the vapor phase material is supplied is switched from the first chamber to the second chamber so that the pressure of the vapor phase material in the material line is kept substantially constant.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: January 11, 2005
    Assignee: Fujitsu Limited
    Inventors: Shigeyoshi Umemiya, Kenji Maruyama
  • Patent number: 6841450
    Abstract: The present invention provides an annealed wafer manufacturing method using a heat treatment method causing no change in resistivity of a wafer surface even when a silicon wafer having boron deposited on a surface thereof from an environment is subjected to heat treatment in an insert gas atmosphere and enabling the heat treatment in an ordinary diffusion furnace not requiring a sealed structure for increasing airtightness nor any specific facility such as explosion-proof facility. The present invention also provides an annealed wafer in which a boron concentration in the vicinity of a surface thereof is constant and crystal defects are annihilated.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: January 11, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Makoto Iida