Patents Examined by Olivia T. Luk
  • Patent number: 6773935
    Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for rapid inspecting of bumps and other three dimensional (3D) features on wafers, other semiconductor substrates and other large format micro topographies. The sensor eliminates out of focus light using a confocal principal to create a narrow depth response in the micron range.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 10, 2004
    Assignee: August Technology Corp.
    Inventors: Cory Watkins, David Vaughnn, Alan Blair
  • Patent number: 6774048
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: August 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyung Baek, Sun-Hoo Park, Hong-Gun Kim, Kyung-Joong Yoon
  • Patent number: 6767843
    Abstract: Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer by oxidizing the silicon carbide layer in an N2O environment. A predetermined temperature profile and/or a predetermined flow rate profile of N2O are provided during the oxidation. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: July 27, 2004
    Assignee: Cree, Inc.
    Inventors: Lori A. Lipkin, Mrinal Kanti Das, John W. Palmour
  • Patent number: 6767752
    Abstract: A temperature control method is provided which is capable of maintaining the accuracy of control based on a detected value of a temperature sensor substantially constant regardless of a change in an error of measurements of the temperature sensor. Measured values of thermocouples 7A, 7B, 7C of a thermocouple thermometer and those of sensor members 6A, 6B, 6C of a radiation thermometer 6 of a sheet-feed apparatus are detected as the processing proceeds. A temperature control parameter of the sheet-feed apparatus is made to change based on differences between the detected temperature values as the processing proceeds.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 27, 2004
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Minoru Nakano, Masaaki Ueno
  • Patent number: 6767845
    Abstract: A method of manufacturing a semiconductor device in which a thin film is formed on a semiconductor substrate using a reaction gas described in the present invention as active species is disclosed, where a film formation process is subdivided into multiple stages and a film is formed by varying the gas pressure or the gas flow speed of the active species within a reaction chamber for each stage.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: July 27, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Naoki Nakamura
  • Patent number: 6767844
    Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: July 27, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd
    Inventor: Chuan-Chieh Huang
  • Patent number: 6759254
    Abstract: A preferred embodiment includes a method for monitoring the performance of a filter positioned in an airstream in a semiconductor processing system. The method includes sampling the airstream at a location upstream of the filter to detect the molecular contaminants present in the airstream; identifying a target species of the contaminants upstream; selecting a non-polluting species of a contaminant having a concentration greater than a concentration of the target species; measuring the non-polluting species in the airstream at a plurality of locations; and determining the performance of the filter with respect to the target species from measurements of the non-polluting species. The plurality of locations includes a location downstream of the filter and at a location within the filter. Further, the method for monitoring includes generating a numerical representation of a chromatogram of the airstream sampled at a location upstream of the filter.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: July 6, 2004
    Assignee: Extraction Systems, Inc.
    Inventors: Oleg P. Kishkovich, Devon Kinkead, Mark C. Phelps, William M. Goodwin
  • Patent number: 6746882
    Abstract: The present invention is generally directed to various methods of correcting non-linearity in metrology tools, and a system for performing same. In one illustrative embodiment, the method comprises creating a non-linear model of measurement data produced by a metrology tool when measuring a plurality of features, each of which has a different, known feature size, measuring a production feature using the metrology tool to produce metrology data for the production feature, determining a correction factor to be applied to the metrology data for the production feature by comparing the non-linear model to a linear model, and applying the determined correction factor to the metrology data for the production feature.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 8, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Broc Stirton, Kevin R. Lensing
  • Patent number: 6746967
    Abstract: A technique in accordance with the invention includes obtaining a semiconductor structure that has a metal disposed thereon. At least a portion of the metal is etched using an etching fluid while sonic energy is applied to the etching fluid.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: June 8, 2004
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Boyan Boyanov
  • Patent number: 6743737
    Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: June 1, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Wai-Fan Yau, David Cheung, Nasreen Gazala Chopra, Yung-Cheng Lu, Robert Mandal, Farhad Moghadam
  • Patent number: 6740571
    Abstract: A method is provided for advantageously etching dielectric material between highly integrated polysilicon devices with high dielectric-to-polysilicon selectivity to expose polysilicon with minimal polysilicon loss and without photoresist lift. A wet etch solution comprising surfactant and between about 0% and about 10% NH4F is used to wet etch the dielectric material and reduce polysilicon loss thickness, polysilicon resistance ratios, and polysilicon etch rates, while increasing dielectric-to-polysilicon selectivity. Advantageously, the present invention may penetrate into increasingly small geometries of highly integrated devices and may also be used for general wet etches of dielectric material in conjunction with photoresist.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: May 25, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventor: Hua Ji
  • Patent number: 6737361
    Abstract: A system and method for conserving and/or recycling hydrogen used in processing operations. The present invention can be used with any conventional reactor, which supports semiconductor processes using hydrogen. Hydrogen is pumped into the reactor from a hydrogen gas supply chamber. The hydrogen is used in the reactor as needed to perform the process function. The hydrogen accompanied with other process gases is exhausted from the reactor. The exhausted gases are routed through a scrubber, which is used to separate the hydrogen from the other gases. The other gases are allowed to vent from the system in a typical manner. The hydrogen is then pumped through an H2 purifier, which cleans the hydrogen gas making the gas once again useable in the semiconductor process.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: May 18, 2004
    Assignee: WaferMaster, Inc
    Inventor: Woo Sik Yoo
  • Patent number: 6720271
    Abstract: The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: April 13, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Bellandi, Francesco Pipia, Mauro Alessandri
  • Patent number: 6716650
    Abstract: For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eckhard Langer, Frank Koschinsky, Volker Kahlert, Peter Hübler
  • Patent number: 6713402
    Abstract: Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and an inert gas in a plasma cleaning chamber following etch-stop etching.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia Beauregard Smith, Heungsoo Park
  • Patent number: 6703316
    Abstract: A method and system for processing a substrate includes performing a wet process by supplying a working liquid to a substrate in a wet processing apparatus, transferring the substrate in a non-dry state from the wet processing apparatus to a drying apparatus, and subjecting the substrate to a supercritical drying by a supercritical fluid in the drying apparatus.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: March 9, 2004
    Assignees: Kabushiki Kaisha Kobe Seiko Sho, Dainippon Screen Mfg. Co., Ltd.
    Inventors: Yoichi Inoue, Yoshihiko Sakashita, Katsumi Watanabe, Nobuyuki Kawakami, Takahiko Ishii, Yusuke Muraoka, Kimitsugu Saito, Tomomi Iwata, Ikuo Mizobata, Takashi Miyake, Ryuji Kitakado
  • Patent number: 6682945
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 27, 2004
    Assignee: AEHR Test Systems
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerzy Lobacz
  • Patent number: 6677250
    Abstract: The invention includes a method of forming a layer on a semiconductor substrate that is provided within a reaction chamber. The chamber has at least two inlet ports that terminate in openings. A first material is flowed into the reaction chamber through the opening of a first of the inlet ports. At least a portion of the first material is deposited onto the substrate. The reaction chamber is purged by flowing an inert material into the reaction chamber through the opening of a second of the inlet ports. The inert material passes from the opening and through a distribution head that is positioned within the reaction chamber between the first and second openings. A second material can then be flowed into the chamber through an opening in a third inlet port and deposited onto the substrate. The invention also includes a chemical vapor deposition apparatus.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: January 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Philip H. Campbell, Craig M. Carpenter, Ross S. Dando, Kevin T. Hamer
  • Patent number: 6673637
    Abstract: Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The measurement device may include an illumination system and a detection system. The illumination system and the detection system may be configured such that the system may be configured to determine multiple properties of the specimen. For example, the system may be configured to determine multiple properties of a specimen including, but not limited to, a presence of macro defects and overlay of a specimen. In this manner, a measurement device may perform multiple optical and/or non-optical metrology and/or inspection techniques.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: January 6, 2004
    Assignee: KLA-Tencor Technologies
    Inventors: Dan Wack, Ady Levy, Kyle A. Brown, Gary Bultman, Mehrdad Nikoonahad, John Fielden
  • Patent number: 6649428
    Abstract: Semiconductor chips mounted in a laminated manner on a substrate and a semiconductor integrated circuit device using the semiconductor chips. A predetermined semiconductor chip is selected by chip selection signals from an external unit despite the chips having the same wiring pattern are laminated in a plural number one upon the other. The semiconductor integrated circuit device is fabricated by using such semiconductor chips.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: November 18, 2003
    Assignee: Fujitsu Limited
    Inventor: Mutsuaki Kai