Abstract: A thin-film forming method applied in an IC manufacturing process is disclosed. The thin-film forming method is used for forming a thin film on a topographically rugged substrate with an improved evenness. The method is characterized in that after a depositing step for forming the thin film is finished, the thin film is continuously ion bombed for a specific time to improve the evenness of the thin film.

Abstract: The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Abstract: The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.

Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.

Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10W to about 500W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A method of making a high quality optical waveguide substrate is provided, in which the surface of a silicon substrate is oxidized through relatively large thickness and no foreign matter particles are adhered on the surface thereof. The silicon substrate to form a quartz film for the optical waveguide is mounted on a carbon contained ceramics sample base and is inserted into a carbon contained ceramics furnace core tube of which its external circumference is arranged in a heating furnace. When the inside of the furnace core tube is heated to 200 to 600° C. by the heating furnace, an oxidant gas for the silicon substrate surface is introduced, then by further heating up to 1200 to 1350° C., the silicon surface is thus oxidized.

Abstract: The invention is a method for forming a flattened interlayer insulating film covering a wiring layer or the like of a semiconductor IC device, and a method of manufacturing a semiconductor device. The film-forming method includes the steps of preparing a deposition gas containing an inert gas, and a silicon and phosphorus-containing compound having III valance phosphorus in which at least one oxygen is bonded to the phosphorous, and forming a silicon containing insulating film containing P2O3 on a substrate by using the deposition gas.

Abstract: A method of determining electrical parameters of a silicon-on-insulator wafer. In this method a native oxide of a silicon layer on a silicon-on-insulator substrate is removed from a silicon mesa formed on the silicon layer. The mesa is contacted with two liquid metal electrodes. A voltage is applied to an electrode on the bottom of the silicon-on-insulator wafer. The current between the two liquid metal electrodes is measured for a combination of voltages between the liquid metal electrodes and the bottom voltage. The resulting current-voltage behavior is analyzed to obtain parameters of mobility, charge in the buried oxide of the silicon-on-insulator substrate, interface state charge, threshold voltages in the linear and saturated regions, doping density, transconductances and output conductances.

Abstract: A silicon substrate including an impurity doped thereinto is raised in temperature to a predetermined annealing temperature, and then the temperature of the silicon substrate reaching the annealing temperature is decreased at variable speeds such that the temperature is decreased at a high speed initially and a low speed latterly. The temperature of the silicon substrate is decreased at such a speed as the impurity with a reduced solid solubility due to the decreased temperature is not acted upon by thermal energy to disconnect the impurity from the silicon substrate.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also include depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.

Abstract: A method of detecting and monitoring elastic strains in a semiconductor wafer (12) comprising the steps of coupling the wafer (12) to a transducer (10) having a periphery (11). This is followed by operating the transducer (10) to produce ultrasonic vibrations at a predetermined wavelength &lgr; and propagating a standing wave through the wafer (12) in response to the ultrasonic vibrations. The method is characterized by extending the wafer (12) in a cantilevered section L from the periphery (11) of the transducer (10) to a distal end (13), and measuring the amplitude of the standing wave &lgr; in the cantilevered section L. For maximum efficiency, the cantilevered section L is substantially one quarter of the predetermined wavelength (&lgr;/4).

Abstract: A method of coupling a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: A method for reducing surface hump phenomena of a doped amorphous silicon layer. A dielectric layer is formed on the device, and subsequently, is patterned to form openings for exposure of the electrode surface of the device. A first deposition step is performed to form a conformal first doped amorphous silicon layer in the opening and on the dielectric layer. A second deposition step is performed to form an undoped or a lightly doped amorphous silicon layer on the first doped amorphous silicon layer and filling the openings completely. A third deposition step is performed to form a second doped amorphous silicon layer on the undoped or a lightly doped amorphous silicon layer.

Abstract: A method for resist strip and metal contamination removal. Wafers (108) with a patterned resist formed thereon are subjected to an ozonated deionized water solution, such as mist (120). The ozonated deionized water solution (120) strips the resist and removes the resist residue. At the end of the process, HCl (152) is added to the deionized water (116) prior to forming the ozonated deionized water solution (120) to remove metal contaminants.

Abstract: Method for characterization of Laterally Diffused Metal Oxide Semiconductors (LDMOS) at the die reference plane. An LDMOS device is epoxied to a midsection for connection to a test fixture for characterization. The combined physical parameters of the LDMOS device and test fixture are determined. Next, the measurements obtained are adjusted for the physical parameters of the test fixture alone, isolating the physical parameters characterizing the LDMOS device at the die reference plane.

Abstract: In a method for heat treatment of silicon wafers under a reducing atmosphere utilizing an RTA apparatus, in particular, microroughness on silicon wafer surfaces is reduced, thereby improving electric characteristics such as oxide dielectric breakdown voltage and mobility of carriers, and generation of slip dislocations and heavy metal contamination are suppressed. Thus, improvement of yield and productivity, and cost reduction are contemplated. According to the present invention, there is provided a method for heat treatment of a silicon wafer under a reducing atmosphere containing hydrogen using a rapid heating/rapid cooling apparatus, wherein a natural oxide film on a silicon wafer surface is removed, and then the silicon wafer is subjected to a heat treatment under an atmosphere of 100% hydrogen or an inert gas atmosphere containing 10% or more of hydrogen using a rapid heating/rapid cooling apparatus.

Abstract: A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.