Patents Examined by P. Hassanzadeh
  • Patent number: 6988463
    Abstract: An ion source is provided wherein depositing gas and/or maintenance gas is/are introduced into the ion source via the vacuum/depositing chamber, thereby reducing the amount(s) of undesirable insulative build-ups on the anode and/or cathode of the source in an area proximate the electric gap between the anode and cathode. In certain embodiments, an insulative and/or dielectric insert(s) and/or layer(s) is/are provided in at least part of an area between the anode and cathode so as to help reduce undesirable insulative build-ups on the anode and/or cathode. More efficient ion source operations is thus achievable.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: January 24, 2006
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Rudolph Hugo Petrmichl
  • Patent number: 6969474
    Abstract: The surface of a device that is surgically implantable in living bone is prepared. The device is made of titanium with a native oxide layer on the surface. The method of preparation comprises the steps of removing the native oxide layer from the surface of the device and performing further treatment of the surface substantially in the absence of unreacted oxygen.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: November 29, 2005
    Assignee: Implant Innovations, Inc.
    Inventor: Keith D. Beaty
  • Patent number: 6953533
    Abstract: A method for removing a chromide coating from the surface of a substrate is described. The coating is treated with a composition which includes an acid having the formula HxAF6, where “A” can be Si, Ge, Ti, Zr, Al, or Ga; and x is 1–6. An exemplary acid is hexafluorosilicic acid. The composition may also include a second acid, such as phosphoric acid or nitric acid. In some instances, a third acid is employed, such as hydrochloric acid. A related repair method for replacing a worn or damaged chromide coating is described. The coating is often applied to portions of turbine engine components made from superalloy materials.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: October 11, 2005
    Assignee: General Electric Company
    Inventors: Lawrence Bernard Kool, Kenneth Burrell Potter, William Randall Thompson, David Carr, Kiyokazu Watanabe, Minoru Ishida, Kazuharu Hattori
  • Patent number: 6936182
    Abstract: A method and system of imagewise etching the surface of a substrate, such as thin glass, in a parallel process. The substrate surface is placed in contact with an etchant solution which increases in etch rate with temperature. A local thermal gradient is then generated in each of a plurality of selected local regions of a boundary layer of the etchant solution to imagewise etch the substrate surface in a parallel process. In one embodiment, the local thermal gradient is a local heating gradient produced at selected addresses chosen from an indexed array of addresses. The activation of each of the selected addresses is independently controlled by a computer processor so as to imagewise etch the substrate surface at region-specific etch rates. Moreover, etching progress is preferably concurrently monitored in real time over the entire surface area by an interferometer so as to deterministically control the computer processor to image-wise figure the substrate surface where needed.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: August 30, 2005
    Assignee: The Regents of the University of California
    Inventor: Michael C. Rushford
  • Patent number: 6936181
    Abstract: The current invention is directed to a method of patterning a surface or layer in the fabrication of a micro-device. In accordance with a preferred embodiment of the invention, a first mask structure is formed by depositing a layer of a first material onto the surface or layer and embossing the layer with a micro-stamp structure. The layer is preferably embossed as a liquid, which is solidified or cured to form the first mask structure. The first mask structure can be used as an etch-stop mask which is removed in a subsequent processing step or, alternatively, the first mask structure can remain a functional layer of the micro-device. In further embodiments, unmasked regions of the surface or layer are chemically treated through the first mask structure and/or a second material is deposited onto the unmasked regions of the surface or layer through the first mask structure to form a second mask structure and/or a second functional layer of the micro-device.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: August 30, 2005
    Assignee: Kovio, Inc.
    Inventors: Colin Bulthaup, Chris Spindt
  • Patent number: 6936135
    Abstract: A confinement ring coupling arrangement for coupling, in a plasma processing chamber, a confinement ring to a plunger. The plunger is configured to move the confinement ring to deploy and stow the confinement ring to facilitate processing of a substrate within the plasma processing chamber. The confinement ring coupling arrangement includes a hanger adapter having a locking head, the hanger adapter being configured to be coupled with the plunger. The confinement ring coupling arrangement further includes a hanging bore disposed in the confinement ring and configured to receive the locking head and to secure the locking head within the hanging bore during stowing and deployment of the confinement ring, wherein a diameter of the locking head is sufficiently smaller than a cross-section dimension of the hanging bore to prevent a sidewall of the locking head from scraping against a sidewall of the hanging bore during the stowing and deployment of the confinement ring.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: August 30, 2005
    Assignee: Lam Research Corporation
    Inventor: Jerrel K. Antolik
  • Patent number: 6926800
    Abstract: A plasma etching apparatus for etching semiconductor wafers. The plasma etching apparatus has a reaction tube made of a dielectric material and a high frequency antenna located around the reaction tube for generating a plasma inside the reaction tube. The high frequency antenna has a sloped segment that produces a relatively large capacitive coupling with the reaction tube. The high frequency antenna is moved by a driver around the reaction tube in a horizontal plane.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: August 9, 2005
    Assignee: Fujitsu Limited
    Inventors: Yuuichi Tachino, Minoru Suzuki, Koji Ibi, Genichi Komuro, Yoichi Okita
  • Patent number: 6923885
    Abstract: A plasma processing apparatus having a sample bench located in a vacuum chamber, a structure disposed at a position opposed to a sample placed on the sample bench and facing a plasma generated in the vacuum chamber, and at least one through-hole disposed in the structure through which a gas flows into the vacuum chamber. An optical transmitter is mounted on a back of the at least one through-hole through which light from the sample passes, which light is detected by way of the optical transmitter.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: August 2, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Masuda, Tatehito Usui, Mitsuru Suehiro, Hiroshi Kanekiyo, Hideyuki Yamamoto, Kazue Takahashi, Hiromichi Enami
  • Patent number: 6921494
    Abstract: A scrubber device is provided. The scrubber device may etch a backside of a wafer and may clean a frontside of the wafer simultaneously. The scrubber device may comprise a programmed controller adapted to supply a non-etching fluid to a frontside of the wafer whenever an etching fluid is supplied to the backside of the wafer.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: July 26, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Brian J. Brown, Madhavi Chandrachood, Radha Nayak, Fred C. Redeker, Michael Sugarman, John M. White
  • Patent number: 6921455
    Abstract: A polishing machine for a peripheral edge of a semiconductor wafer comprises a rotary mechanism 2 which rotates a stack 1 of semiconductor wafers 4 mounted thereon, and a polishing mechanism 3 which is arranged to be movable in the radial direction of the rotary mechanism 2 and polishes the peripheral edges of the rotating semiconductor wafers 4 by means of contactless polishing. Minute gaps s are formed between the rotary column 10 of the polishing mechanism 3 and the stack 1 of semiconductor wafers 4, and polishing solution is drawn into these minute gaps s. The peripheral edges of the semiconductor wafers 4 are polished by means of contactless polishing, using polishing abrasive particles included in polishing solution.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: July 26, 2005
    Assignee: Kabushiki Kaisha Ishii Hyoki
    Inventors: Teruyuki Nakano, Yasuhiro Kozawa, Hitoshi Tambo
  • Patent number: 6916429
    Abstract: A process for removing aluminosilicate-based material (e.g., “CMAS”) from a substrate is described. The material is treated with an aqueous composition containing at least one acid having the formula HxAF6, in which A is Si, Ge, Ti, Zr, Al, and Ga; and x is 1-6. Treatment of the substrate is often carried out by immersion in an aqueous bath. The process is also very effective for removing CMAS-type material from cavities in the substrate, e.g., cooling holes in a gas turbine component. Related compositions are also described.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: July 12, 2005
    Assignee: General Electric Company
    Inventors: Lawrence Bernard Kool, Stephen Joseph Ferrigno, Robert George Zimmerman, Jr., Mark Alan Rosenzweig, Curtis Alan Johnson
  • Patent number: 6916401
    Abstract: A segmented electrode apparatus for use in plasma processing in a plasma chamber or as part of a plasma processing system. The apparatus is composed of a plurality of electrode segments each having an upper surface, a lower surface and a periphery. The lower surfaces of the electrode segments define an electrode segment plane. Further included in the electrode is a plurality of displaceable insulating ring assemblies with a conductive shielding layer in each of them. Each assembly has an insulating body with an upper and lower portion and surrounds a corresponding one of the electrode segments at the electrode segment periphery. Each insulating ring assembly is arranged adjacent another insulating ring assembly and is displaceable with respect thereto and to the corresponding electrode segment. Also included in the electrode apparatus is a plurality of displacement actuators connected to the chamber and to the plurality of insulating ring assemblies at the insulating body upper portions.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: July 12, 2005
    Assignee: Tokyo Electron Limited
    Inventor: Maolin Long
  • Patent number: 6913670
    Abstract: A substrate support has a receiving surface capable of receiving a substrate during processing in a substrate processing chamber. The substrate support has a pedestal having a conduit to circulate a heat transfer fluid therein. A barrier about the conduit includes a fluid detection material capable of detecting a leakage of the fluid from the conduit be changing an attribute, for example, an optical or electrical property.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: July 5, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Kadthala R. Narendrnath, Michael Douglas, Surinder Bedi
  • Patent number: 6905571
    Abstract: When honing an abrasive pad for polishing a wafer by rotating while closely contacting the wafer by bringing a conditioner into contact with the abrasive pad, forces applied from the abrasive pad to the conditioner are detected by a plurality of pressure detectors through a conditioner driving unit for holding the conditioner. The pressure detectors are respectively able to detect forces in two directions such as rotational direction and radial direction. A memory stores correlations between detection values and wafer polishing quantities under various conditioning terms. Therefore, it is determined whether the detection values are kept within acceptable limits stored in the memory. When the values are out of the acceptable limits, a controller controls the values so that they fall within the acceptable limits by properly changing conditioning terms.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 14, 2005
    Assignee: Elpida Memory, Inc.
    Inventors: Noriyuki Sakuma, Kinji Tsunenari
  • Patent number: 6887391
    Abstract: MEMS structures may be formed on a substrate by forming a series trenches filled with etch-stop material in the device layer, followed by an isotropic etch of the device material stopping on the etch-stop material. This approach provides a controlled release method where the exact timing of the isotropic release etch becomes non-critical. Further, using this method, structures with significant topology may be fabricated while keeping the wafer topology to a minimum during processing until the very end of the process. Using the method of this invention, features with large topology may be formed while keeping the wafer topology to a minimum until the very end of the process.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: May 3, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Michael J. Daneman, Behrang Behin
  • Patent number: 6887317
    Abstract: A substrate support is provided that features a lift pin having at least one larger diameter shoulder section that forms a relief region between the lift pin and a guide hole disposed through a substrate support. The shoulder section minimizes contact between the substrate support and lift pin guide hole, thereby reducing pin scratching, particle generation, component wear, and increasing the useful life of the pin. In another embodiment, a flat-bottom tip is provided to promote self-standing of the lift pin, reducing pin tilting or leaning of the lift pin within the guide hole.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: May 3, 2005
    Assignee: Applied Materials, Inc.
    Inventors: David T. Or, Keith K. Koai, Hiroyuki Takahama, Takahiro Ito, Koji Ota, Hiroshi Sato
  • Patent number: 6878296
    Abstract: A printed wiring board having a conductor pattern on which a pre-flux film of a stabilized quality is to be formed using a water-soluble pre-flux liquid. To this end, such an apparatus is used which includes an etching unit 12 for etching lands 5b, 6b formed on the printed wiring board 1, a rinsing unit 13 for rinsing the printed wiring board 1, a bubble removing unit 14 for removing air bubbles 58 attached to the printed wiring board 1 on immersing the printed wiring board 1 in a water-soluble pre-flux liquid 9a in a processing vessel 56, a pre-flux forming unit 15 for forming a pre-flux film 9 on the lands 5b, 6b of the printed wiring board 1 in the pre-flux liquid 9a using an in-liquid spraying unit 61, a liquid removing unit 16 for removing the pre-flux liquid 9a from the printed wiring board 1 transported from the processing vessel 56 and a rinsing unit 17 for rinsing the printed wiring board 1.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: April 12, 2005
    Assignee: Sony Corporation
    Inventors: Atsuhiro Uratsuji, Tatsutoshi Narita, Masanobu Yagi, Yoshiyuki Ukeda
  • Patent number: 6872280
    Abstract: A slurry collection device 1 includes a ring-shaped barrier member 2 provided around a turntable T of a polishing machine E and a ring-shaped slurry collection container 3 provided around the barrier member 2. The turntable T is connected to an upper end of a main rotation shaft T1 that sticks out from a bottom portion of a sink S of the polishing machine E and is lifted from the bottom portion of the sink S. The slurry collection device 1 of the present invention is inserted between the turntable T and the sink S.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: March 29, 2005
    Assignee: International Business Machines Corporation
    Inventors: Shunsuke Tanaka, Masami Shinohara, Kohichi Ishimoto
  • Patent number: 6863770
    Abstract: A method and apparatus for polishing a substrate with a polishing pad and slurry entails washing polishing-pollutants produced by the polishing operation off of the pad in such a way that the pollutants are not splashed onto components of the polishing apparatus. A washing solution for removing the pollutants is directed onto the polishing pad as at least one free-flowing vertical stream. Because the washing solution flows freely and vertically as it impinges the polishing pad, the washing solution does not rebound from the pad and flows from the surface of the polishing pad without causing the pollutants on the pad to be splashed up from the surface of the pad.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: March 8, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Man-Ho Jae, Min-Gyu Kim
  • Patent number: 6860964
    Abstract: An integrated etch/strip/clean apparatus is disclosed. The apparatus includes an etching line to etch and clean a substrate, a stripping line to strip the etched substrate, and a cleaning line to clean and dry the substrate. The cleaning line is on the stripping line. Accordingly, etch, strip and cleaning processes is performed by a single equipment. As a result, processing time installation space requirement of the equipment are reduced. Further, contamination of the substrate is prevented.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: March 1, 2005
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Il Ryong Park