Abstract: This invention discloses an apparatus for a global network communicator including an application-specific communications device suitable substantially only for global network communications and including a global network application specific user interface, network protocol processing circuitry operative for communication with the global network and for formatting data to a required protocol employed by the global network and for translating data received from the global network to a format acceptable to the user interface, a communication line interface interconnecting the network protocol processing circuitry to the global network and including logical and physical interface apparatus and modulation and demodulation apparatus for information transmitted to the global network and information received from the global network respectively and network access activation circuitry for initiating communication between the communicator and the global network.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: An apparatus and method for scheduling data transfers between a host and adapter. A schedule table data structure resides in a memory on the adapter. Each location in the schedule table represents a point in time at which data is to be transmitted from the adapter. A current time counter advances at the rate at which data is to be transmitted from the node. A pointer points to successive locations in the schedule table, and advances through the schedule table at a rate faster than the current time counter advances so that the value stored in the pointer represents a point in time which is ahead of the point in time currently represented by the value output from the current time counter. A request for a data transfer between the host and adapter is generated when a valid entry exists at the location pointed to by the pointer. The value of the pointer at the time the request is generated is stored as the last valid time.

Abstract: A method and apparatus for providing stricter data types, and stricter data type checking, in a data flow diagram. For numeric data types, a unit data type is associated with the data type. Therefore, if a user desires to change the units from one compatible type to another, such as feet to meters, this can be done without recompilation. Unit type checking is also provided, whereby, as a block diagram is created, the block diagram editor continually checks each node or function for impermissible data unit operations. This provides a more powerful debugging environment than that previously known in the art. Polymorphic unit capabilities are also provided whereby a virtual instrument can perform calculations regardless of unit but also has unit type checking capabilities. A stricter data type referred to as the enumerated data type is also included which is a variation of an integer numeric data type that includes an enumerated list of mnemonics.

Abstract: An apparatus employs a flexible instruction categorization scheme which includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instructions are conveyed to multiple functional units, each of which perform a portion of the multiple dispatch instruction. A predefined fixed number of functional units are employed to execute a multiple dispatch instruction, allowing for additional instructions to be dispatched concurrently with the multiple dispatch instructions. In contrast to multiple dispatch instructions, microcode instructions may occupy a variable number of functional units and may dispatch instructions for a variable number of clock cycles. Additionally, multiple instruction operations may be performed in a given functional unit in response to an instruction. In one embodiment, up to two instruction operations may be performed in a functional unit.

Abstract: A repeater interface controller ("RIC") integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted.

Abstract: A system and method for dividing execution of an instruction stream among a plurality of tightly coupled instruction execution units is presented. The present invention couples a plurality of instruction execution units tightly and provides a mechanism whereby control may be passed from one instruction execution unit to another instruction execution unit without raising exceptions or terminating normal execution of the instruction stream. The present invention employs a caller instruction execution unit that has a complete parser and the capability to emulate at least a portion of the instruction stream and at least one partial instruction execution unit. The caller instruction execution unit passes control to the partial instruction execution unit and allows the partial instruction execution unit to execute as many instruction of the instruction stream as it can.

Abstract: A program stored within an application memory storage area of a removable system resource has a more than one step and at least one of the steps requires a datum be written to a portion of the application storage area. The program is executed from the removable resource. A page table is built which has one page entry per page of the program. A given page entry maps a physical address for the page corresponding to the page entry to a virtual address for the corresponding page. Each page entry of the page table is marked to indicate that the page corresponding to the page entry has a read-only status. The program is then executed step-by-step. When the step requiring the datum to be written to the application storage area occurs, a faulting page is determined. The faulting page is the page that contains the portion of the application storage area to which the datum is to be written.

Abstract: A digital processor enables data to be read from an external memory without losing arithmetic processing efficiency. A coefficient memory 16, a general-use memory 20, an arithmetic logic unit 26, a sum of products computer 28, a program memory 32, and a host interface circuit 34 are coupled to a data bus 10. A data memory 18, the general-use memory 20, an external memory input/output interface circuit 22, an audio/interface circuit 24, the arithmetic logic unit (ALU) 26, and the sum of products computer 28 are coupled to another data bus 12. The general-use memory 20, the external memory input/output interface circuit 22, and the arithmetic logic unit 26 are coupled to a general data bus 14.

Abstract: Collision delay intervals are modified in Ethernet network devices by transmitting priority data requiring a guaranteed latency by determining an integer multiple number of slot times, randomly selected from a predetermined range of integers, where the range of integers is independent from the number of access attempts. A network device having priority data for transmission randomly selects a collision delay interval to be either zero or one slot time for a predetermined number of access attempts. If the number of collisions encountered by the network station exceeds the predetermined number, the integer is selected from a range of integers calculated from a shifted exponential number of the access attempts, resulting in a smaller range than used for normal priority traffic.

Abstract: A prediction storage for branch predictions and information corresponding to branch instructions which are outstanding within an instruction processing pipeline of a microprocessor. A branch tag is assigned to each branch instruction and the corresponding branch prediction and prediction information is stored into the prediction storage. The branch tag is routed through the instruction processing pipeline with the branch instruction. Branch prediction information corresponding to the instruction remains within the branch prediction storage apparatus, which may be integrated into a branch predictor or coupled nearby. The branch tag may be more easily routed through the pipeline since the branch tag may include fewer bits than the corresponding branch prediction information. The branch prediction information may be updated after correct or incorrect prediction by conveying an indication of the prediction or misprediction and the branch tag of the branch instruction to the branch prediction storage apparatus.

Abstract: A framework having a plurality of directories representing different types of middlewares and distributed object systems can be constructed from data provided in a class library. Each directory includes the name and address of all service objects, located across multiple servers in the system, that supports the specific middleware or distributed object policy characteristics for that directory. One service object may be addressed through multiple directories. When a remote method call is issued by a client, a list of service objects capable of executing the call is obtained from the directories and one object selected. The policy characteristics associated with the directory from which the object address is selected, are attached to the call. These characteristics are validated when the addressed server receives the call. In this way, a client program can be written entirely independently of the middleware or peculiarity of implementation of the distributed object service.

Abstract: A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called "packed instructions". Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganised within a data string thereby minimising loading and storing operations to memory.

Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.

Abstract: A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information characterizing the data transfer operation. In response to the byte order information and the data transfer operation information, the control unit generates a control signal that is coupled to a BPU. The control signal causes the BPU to rearrange the order of bytes in the data being transferred when the byte order information indicates a first byte ordering format. When the byte order information indicates a second byte ordering format, the BPU does not change the order of the bytes in the data being transferred.

Abstract: An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed.

Abstract: A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction. Branch instructions may be scheduled distant from the instruction which sets the condition flags tested by the branch instruction. Numerous instructions may be placed between the two instructions, such that the condition flags may be available at the time the instruction is fetched. The branch instruction may be executed without stalling until the condition flags are available. In another embodiment, the branch prediction unit is configured to predict the direction a branch instruction may take according to a branch prediction scheme. Additionally, upon detection of a segment override prefix byte, the branch prediction unit uses an alternative branch prediction scheme.

Abstract: The invention is a method and apparatus for conditionally nullifying a current instruction based on a first test value where the first test value can be set in one or more prior instructions and where the execution of the current instruction can set a second test value without affecting the first test value. The one or more prior instructions which set the first test value need not immediately precede the current instruction. In a preferred embodiment, a test value comprises multiple bits, each bit capable of representing a unique state. A mask is provided to select the bits which are being tested. Also, means are provided for specifying an logical operation to be performed on the test values. The invention permits multiple status test results to be saved and concurrently tested in a single branch instruction.

Abstract: Method and apparatus for altering an executable file stored in a random access memory on a designated interactive network having a local area network interface comprises activating a LAN communication program. The communication program operates to broadcast an inquiry through the local area network for the designated interactive network board, to receive location information of the designated interactive network board in response to the broadcast inquiry, and to establish communication with the designated interactive network board. The executable file is downloaded into RAM on the designated interactive network board through the local area network interface. A verifying step verifies a checksum value of the executable file against a checksum value in a checksum packet attached to the executable file. In the case that the verifying step is successfully completed, execution of the executable file may be commanded remotely, e.g., across the LAN interface.

Abstract: A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The processor further comprises circuitry for forming a microaddress for addressing the microprogram memory. This circuitry includes circuitry (26, 28) for identifying a value of a first bit (A0) and of a second bit (A1), and the microaddress comprises the first bit, the second bit, and a plurality of main bits (20c). Further, the processor includes circuitry for selectively energizing (24, 13a, 13b) a subset of the separately energizable banks in response to the value of the first bit, and the subset is less than the number of separately energizable banks. Still further, the processor includes circuitry (16) for outputting a first set of microinstructions from the subset of the separately energizable banks.