Abstract: A method and system for managing terminals in a network computing system in which a host computer and a plurality of terminals are interconnected via a front-end processor. The front-end processor employs a terminal manager to monitor its subordinate terminals and provide the host computer with terminal information of the terminals in session and an identification number of the front-end processor itself. A subordinate manager disposed in the host computer receives the terminal information and identification number from the terminal manager, and stores them into a subordinate information table for future reference in transactions with the terminals. The front-end processor has extended capability for managing the messages waiting for transmission services in a message queue. The front-end processor provides some functions such as inquiring the host status in advance, rearranging the transmission order, deleting invalidated messages, and redirecting messages to a predetermined alternative address.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: A predecode unit within a microprocessor predecodes a cache line of instruction bytes for storage within the instruction cache of the microprocessor. The predecode unit produces multiple shift amounts, each of which identify the beginning of a particular instruction within the instruction cache line. The shift amounts are stored in the instruction cache with the instruction bytes, and are conveyed when the instruction bytes are fetched for execution by the microprocessor. An instruction alignment unit decodes the shift amounts to locate instructions within the fetched instruction bytes. Each shift amount directly identifies a corresponding instruction for dispatch, and therefore decoding the shift amount directly results in controls for shifting the instruction bytes such that the identified instruction is conveyed to a corresponding issue position. The number of shift amounts stored may be equal to the number of issue positions within the microprocessor.

Abstract: An apparatus and method to manage data flow dependencies so that a processor can complete instructions and write associated data to architected logical registers out of the program order. This increases the commission bandwidth of the processor allowing greater processor throughput, by allowing instructions to pass the completion stage prior to having produced data.

Abstract: A method and apparatus for managing register renaming in an information handling system that supports out-of-order and speculative instruction execution. Register entries are stored in architected registers, and rename entries are stored in rename registers. Register and rename entries are transferred between the rename and architected registers in response to dispatch of instructions or upon the occurrence of a canceling event, such as a mispredicted branch instruction or an interrupt condition. Rename entries are stored in the rename registers in a round robin fashion and tagged by age. Age order of the rename entries is determined without keeping the rename entries in age order through the method of shifting rename entries to the next rename register each time a rename entry is removed from a rename register. By eliminating shifting of rename entries to maintain age order, a power savings is realized.

Abstract: A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation.

Abstract: Apparatus and method for monitoring parameters that govern the operational characteristics of a network device, including the use of templates for generating configuration records of network devices of a selected model type. A database of models is provided, each model representing an associated network device and including attribute values for the parameters of the associated network device. Templates are used to screen a model in order to retrieve values for each of the attributes and create a configuration record. The configuration records may be stored in the configuration manager or other storage device, and/or transferred to the pre-existing model database for use by a network management system in reconfiguring the associated network devices. Additionally, a method and apparatus is provided that defines network groups, defines network policies for groups, determines conflicts, and resolves conflicts among groups and devices.

Abstract: A microcomputer having a function for monitoring internal resources closed within the microcomputer without preventing an execution of the microcomputer. An address of a register within the microcomputer is determined in advance from the outside of the microcomputer, and at a coincident timing with the register address outputted onto an internal register address bus, data on an internal data bus are taken in and are outputted to the outside of the microcomputer via a serial interface. The information of the internal resources closed within the microcomputer can be obtained without stopping the execution of the microcomputer to enable avoiding of a runaway or trouble of a machine to be controlled by the microcomputer and to enable developing at a real time similar to an execution time.

Abstract: A microchip has a register file having a plurality of registers and an accumulator register connected in parallel with the register file that allow write operations to be performed concurrently during a single write cycle. Write operations can include write data to be written to a destination register and identification data designating a destination register. Where a first instruction designates a register in a register file and second instruction designates an accumulator register, write data from the first and second instructions can be written concurrently to the register file and the accumulator register during a single write cycle. By providing an accumulator register that is separate from the register file, data directed toward an accumulator register is diverted away from the register file and delays in performing write operations to the register file are reduced.

Abstract: A policy-driven network traffic manager recommends to individual application programs that generate network traffic whether, and optionally under what conditions, they should generate network traffic. The network traffic manager has an interface, through which the application programs, prior to generating network traffic, call the network traffic manager and describe the traffic the application programs propose to generate. A policy repository stores a set of policies, which the network traffic manager uses to ascertain whether the application programs should generate the proposed network traffic. The policies can include considerations such as time, link cost, latency, congestion and availability. The network traffic manager then sends the recommendations to the application programs.

Abstract: The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only control store 5 for storage of microinstructions. The random access control store includes a flag microinstruction (REPmark1) for indicating that another microinstruction (add W, 2, W1), stored in the read only control store 5, is faulty. The control stores are coupled to a multiplexer 8 and are adapted to output the microinstructions in parallel to the multiplexer 8 which is in turn coupled to the processor and which selectively provides output from either the random access control store or the read only control store to the processor 1. The apparatus also includes a decoder coupled to the random access control store for observing the microinstructions output therefrom. The decoder is further coupled to inhibiting logic in the processor and outputs a signal if the flag microinstruction is output from the random access control store.

Abstract: Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer locations, where N is greater than M. When a fetch within the processor misses the instruction cache, the fetch address is placed in the streaming buffer. When the data has been fetched from the external memory, it is returned to the streaming buffer and placed into one of the M physical buffer locations. The data within the streaming buffer is returned to the instruction cache of the processor only if it is to be used in accordance with the computer program being executed.

Abstract: A telecommunications management network (TMN) is directly connected for operation and maintenance data message exchange to a common channel signaling network. The direct connection to the telecommunications management network is made through a gateway one of a plurality of signal transfer points included within the telecommunications network. Addressing and format conversions are effectuated between the transmission control protocol/internet protocol (TCP/IP) used for the telecommunications management network operation and maintenance messages and the common channel signaling--signaling system no. 7 messages. The telecommunications management network and each of the network element nodes are accordingly assigned both an internet protocol address and a signaling system no. 7 (SS7) address. Static tables maintained in certain ones of the signal transfer points map internet protocol addresses and signaling system no. 7 (SS7) address against each other for message routing.

Abstract: A method for choosing a particular server on a network and performing a remote boot by a client, the network including a plurality of servers operating in accordance with a plurality of network operating systems, includes identifying each of the plurality of servers by address and by type of operating system, and selecting one of the identified servers by address and type for booting on the network. Identifying further includes sending a FIND frame from the client to the network, and receiving a FOUND frame from each of the plurality of servers. A remote program load protocol followed by the server according to the FOUND frame is determined.

Abstract: In a synchronous arbitration unit with round-robin priority for arbitrating between N requests (Ri) for access to common resources of a multiprocessor system, the requests stored in an input register timed by a clock signal are applied as inputs to a fixed-priority arbitration network having 2N-1 inputs, N-1 of the requests being applied both to a first set of N-1 lower-priority inputs of the network and, through masking circuits which selectively mask the requests with a binary masking configuration generated by mask-generating circuits in accordance with predetermined priority-rotation criteria, to a second set of N-1 higher-priority inputs of the network, in the same order of input priority. The grant signals output by the network are latched in an output register after logical OR of the grant signals associated with the same request and the arbitration unit thus formed has a minimal arbitration time and is constituted by a small number of logic components.

Abstract: A method, apparatus and computer program product for reducing the data transmitted over an external communication link using the TCP protocol from a first application resident in a first computer and to a second application resident in a second computer. The method, apparatus and computer program product include establishing a first virtual socket in the first computer in response to each connection request by the first application for receiving request data originated by the first application. A first real socket in the first computer and a second real socket in the second computer are established to connect the first computer to the second computer over the external communication link and are maintained until the request data has been provided to the second application.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.

Abstract: A buffer IC includes two FIFO buffers accessible in a triple-bus configuration including a bi-directional port, an input port, and an output port. Each of the ports uses a fall-through timing which facilitates interconnection of similar buffer ICs into a chain to expand the depth of a FIFO buffer. Typically, the input and output ports have a data width that differs from the data width of the bi-directional bus the FIFO buffers perform bus matching. One type of bus matching collects data values from the smaller width port to form larger width values for output from the larger port. Another type of bus matching splits data values from the larger width port to form data values for output from the smaller port.

Abstract: A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.

Abstract: A device control apparatus includes a request accepting unit which accepts a device control request, the device control request containing an instruction code indicating a specified instruction and a device identifier indicating a specified device. A competition control unit includes a set of competition definition tables for respective devices and respective device-control instructions, reads out one of the competition definition tables by the device control request, and recognizes competition states between in-process instructions to competition devices and the specified instruction to the specified device by using the read-out competition definition table. A parallel execution control unit performs execution of one or a plurality of the specified instruction and the in-process instructions in accordance with the competition states when a sum of a first weight for the specified instruction and a second weight for the in-process instructions is less than a maximum weight.