Patents Examined by Patricia D Valenzuela
  • Patent number: 11948853
    Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 2, 2024
    Assignees: QUALCOMM TECHNOLOGIES INCORPORATED, RF360 EUROPE GMBH
    Inventors: Jose Moreira, Markus Valtere, Juergen Portmann, Jeroen Bielen
  • Patent number: 11950462
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 2, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue, Hiroharu Jinmura, Takeshi Yaneda
  • Patent number: 11942424
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Chih-Chao Yang
  • Patent number: 11942393
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Mitul Modi, Nicholas Neal
  • Patent number: 11935991
    Abstract: A light emitting device includes: a base member having a first surface including a first region; a first electric terminal including a first pin hole, the first pin hole penetrating the base member along a thickness direction of the base member; a second electric terminal including a second pin hole, the second pin hole penetrating the base member along the thickness direction; a first frame provided on the base member and surrounding the first region; a plurality of light emitting elements provided on the base member in the first region; a light-transmissive first member provided inward of the first frame, and covering the plurality of light emitting elements; and a protective element positioned between the base member and the first frame in the thickness direction.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: March 19, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Shinya Okura, Takanobu Sogai, Koji Oshodani
  • Patent number: 11929454
    Abstract: A light emitting device includes: a base member having a first surface including a first region and a second region; a first frame provided on the base member and surrounding the first region; a light emitting element provided on the base member in the first region; a light-transmissive first member provided inward of the first frame, and covering the light emitting element; an electronic component provided on the base member in the second region and electrically connected with the light emitting element; and a plurality of pin holes arrayed in a first direction and electrically connected with the electronic component, the first direction being orthogonal to a thickness direction of the base member. The electronic component is provided on a side opposite the plurality of pin holes with respect to the light emitting element in a second direction that is orthogonal to the thickness direction and the first direction.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 12, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Shinya Okura, Takanobu Sogai, Koji Oshodani
  • Patent number: 11929294
    Abstract: A composite substrate includes a base layer formed of a composite material containing diamond and a metal, the base layer a first surface, and a second surface opposite to the first surface; a flat layer having a lower surface bonded to the first surface of the base layer, and an upper surface having a surface roughness Ra of 10 nm or less; and an insulating layer directly bonded to the upper surface of the flat layer.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 12, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Masatsugu Ichikawa, Shoichi Yamada, Takeshi Kihara, Yutaka Matsusaka
  • Patent number: 11929299
    Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jose Moreira, Markus Valtere, Bart Kassteen, Alberto Jose Teixeira De Queiros
  • Patent number: 11915969
    Abstract: A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.
    Type: Grant
    Filed: March 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Chiang Liu, Hung-Kwei Liao
  • Patent number: 11901305
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Patent number: 11901296
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Kristof Darmawikarta, Sri Ranga Sai Sai Boyapati
  • Patent number: 11901303
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11894304
    Abstract: The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: February 6, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Tsung Wu
  • Patent number: 11894345
    Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 6, 2024
    Assignee: Adeia Semiconductor Inc.
    Inventors: Javier A DeLaCruz, Don Draper, Belgacem Haba, Ilyas Mohammed
  • Patent number: 11894262
    Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow
  • Patent number: 11887904
    Abstract: It is an object to provide technology allowing for improvement in productivity of a semiconductor device. A semiconductor device includes: a base plate; an insulating substrate including a ceramic plate integrally bonded to an upper surface of the base plate with no solder layer therebetween and a circuit pattern disposed on an upper surface of the ceramic plate; a semiconductor element mounted on an upper surface of the circuit pattern; a case surrounding the insulating substrate and the semiconductor element over the base plate; an adhesive to adhere a lower portion of the case to an outer peripheral portion of the ceramic plate; and a sealant to seal the interior of the case, wherein the adhesive is in contact with an outer peripheral end of the ceramic plate to an outer peripheral end of the circuit pattern.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: January 30, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Oya
  • Patent number: 11887930
    Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 30, 2024
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11888041
    Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Megumi Ishiduki, Hiroshi Nakaki, Takamasa Ito
  • Patent number: 11881453
    Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chia-Hsiang Hsu
  • Patent number: 11881451
    Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ching-Cheng Chuang