Abstract: A semiconductor apparatus including a layered structure is disclosed. In one example, a first substrate with a light-emitting element and a second substrate with a light-blocking member on a periphery are layered with each other. The layered structure includes a first resin including a photocurable resin that seals a part between the first substrate and the second substrate in a pixel region. A second resin seals a part between the first substrate and the second substrate in a light-blocking region at a periphery. A protrusion structure is arranged between the first substrate and the second substrate in a boundary region between the pixel region and the light-blocking region, and includes a transparent or semitransparent material that transmits light.

Abstract: The present disclosure provides an organic electroluminescent device and a manufacturing method thereof. The organic electroluminescent device includes an anode, an electron transport layer and a cathode. The material of the electron transport layer includes a mixture of a first electron transport material and a second electron transport material, the lowest unoccupied molecular orbital energy level of the first electron transport material is higher than that of the second electron transport material, and the ratio of the first electron transport material to the second electron transport material first decreases and then increases in the direction from the cathode to the anode.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements. The solid-state image sensor also includes a mosaic pattern layer disposed above the photoelectric conversion elements. The mosaic pattern layer includes an infrared-passing segment and color filter segments disposed on the periphery of the infrared-passing segment. The solid-state image sensor further includes a first condensing structure disposed on the mosaic pattern layer. The infrared-passing segment and the color filter segments share the first condensing structure.

Abstract: The present disclosure relates to a semiconductor device and a preparation method thereof. The method for preparing a semiconductor device comprises: providing a first dielectric layer; forming a first window in the first dielectric layer; forming a first connection structure in the first window; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second window from which at least the first connection structure is exposed; forming a first barrier layer on the sidewall and bottom of the second window, the first barrier layer comprising an opening from which part of the first connection structure is exposed; and forming a second connection structure in the second window.

Abstract: The present invention concerns the use of a mixture of organic peroxides for crosslinking a polyolefin elastomer (POE), in particular intended to be used in photovoltaic applications. The invention also relates to a crosslinkable composition comprising at least one polyolefin elastomer (POE) and at least one mixture of organic peroxides. The present invention also concerns a method for preparing a material made from polyolefin elastomer (POE), preferably an encapsulating material or a sealing agent, in particular for photovoltaic cells, comprising a step of crosslinking a crosslinkable composition as defined previously.

Abstract: An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

Abstract: A light emitting device package according to an embodiment comprises: first and second frames disposed spaced apart from each other; a body disposed surrounding the first and second frames and having first and second openings spaced apart from each other; a light emitting device disposed on the body and including first and second bonding parts; and first and second conductive parts disposed in the first and second openings respectively, wherein the first and second openings perpendicularly overlap the first and second frames respectively, the first and second conductive parts are electrically connected to the first and second frames respectively, the first and second bonding parts are disposed in the first and second openings respectively, and are electrically connected to the first and second conductive parts, and the light emitting device includes a support region disposed on the body outside the first and second openings.

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

Abstract: An InGaN-based LED epitaxial wafer and a fabrication method thereof are disclosed, wherein the InGaN-based LED epitaxial wafer includes: a substrate; an InGaN layer, formed on a surface of the substrate, having an In content between 40% and 90%, so as to ensure that the LED epitaxial wafer is capable of emitting long-wavelength light or near-infrared rays; a p-type metal oxide layer, formed on a surface of the InGaN layer facing away from the substrate, acting as a hole injection layer for the InGaN layer.

Abstract: A semiconductor device includes a substrate, conductive features on the substrate, and a passivation layer over the conductive features to define conductive pads in the respective conductive features through exposed portions of each of the conductive features. Each corner of the conductive pads is free of right angle, the substrate has a pair of long sides from a top view perspective, the shape of each of the conductive pads is a parallelogram. Each of the conductive pads has a pair of long sides and a pair of short sides from a top view perspective, a portion of the conductive pads have the long sides sloped away from a first pad density area of the substrate and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped toward the first pad density area and toward the other long side of the substrate.

Abstract: A plurality of semiconductor chips, a module substrate on which the plurality of semiconductor chips are mounted, a heat sink on which the module substrate is mounted, and a filler filled between the module substrate and the heat sink are included, in which the module substrate includes a heat radiating plate, and an insulating substrate on which the plurality of semiconductor chips are mounted, the heat radiating plate has a plurality of recess portions provided on a surface facing the heat sink and at least one groove, the plurality of recess portions are provided in regions corresponding to below arrangement regions of the plurality of semiconductor chips, the at least one groove is provided in a region corresponding to below a region between at least one of the plurality of semiconductor chips and an adjacent other semiconductor chip, and the filler also is filled in the plurality of recess portions.

Abstract: Provided is a method of fabricating a capacitor. The method of fabricating a capacitor may include forming a first electrode, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, and applying, between the first electrode and the second electrode, a voltage outside an operating voltage range applied during operation or a current outside an operating current range applied during operation.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Abstract: First overlying wires are provided between a display area and a bending portion, extending parallel to each other in a direction crossing the direction in which the bending portion extends. Underlying wires are provided between a first resin layer and a second resin layer on a resin substrate, extending across a slit and parallel to each other in a direction crossing the direction in which the bending portion extends. The first overlying wires are electrically connected respectively to the underlying wires via first contact holes formed through the second resin layer and inorganic insulation films.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.