Patents Examined by Patricia D Valenzuela
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Patent number: 11817366Abstract: A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A first conductive connector is affixed to a first connector pad of the package substrate. A conformal thermal conductive layer is applied on the semiconductor die and a portion of the first surface of the package substrate. The conformal thermal conductive layer is configured and arranged as a thermal conduction path between the semiconductor die and the first conductive connector.Type: GrantFiled: December 7, 2020Date of Patent: November 14, 2023Assignee: NXP USA, INC.Inventors: Michael B. Vincent, Scott M. Hayes, Zhiwei Gong, Kabir Mirpuri, Rushik P. Tank, Betty Hill-Shan Yeung
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Patent number: 11810815Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.Type: GrantFiled: April 26, 2022Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee, Ting-Ya Lo
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Patent number: 11810835Abstract: An intelligent power module packaging structure includes an insulated heat dissipation substrate, a plurality of power devices, a control chip, a lead frame, and an encapsulant. The insulated heat dissipation substrate has a first surface and a second surface opposite to the first surface. The power devices are disposed on the first surface. The control chip is disposed on the first surface. The control chip provides a gate driver function for driving the power devices and a pulse width modulation function. The lead frame is bonded onto the first surface. The power devices are electrically connected to the control chip and the lead frame. The encapsulant at least encapsulates the power devices, the control chip, and a portion of the lead frame, and the second surface is entirely or partially exposed outside the encapsulant.Type: GrantFiled: October 28, 2020Date of Patent: November 7, 2023Assignee: ACTRON TECHNOLOGY CORPORATIONInventors: Hsin-Chang Tsai, Ching-Wen Liu
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Patent number: 11810851Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.Type: GrantFiled: February 28, 2022Date of Patent: November 7, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hitoshi Okano, Hiroyuki Kawashima
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Patent number: 11804439Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.Type: GrantFiled: May 16, 2022Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
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Patent number: 11804432Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.Type: GrantFiled: February 11, 2021Date of Patent: October 31, 2023Assignee: Infineon Technologies AGInventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
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Patent number: 11791288Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: GrantFiled: April 27, 2022Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Erik Nino Tolentino, Yusheng Lin, Swee Har Khor
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Patent number: 11791246Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.Type: GrantFiled: April 21, 2022Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
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Patent number: 11784285Abstract: A three-dimensionally structured semiconductor light emitting diode includes a first conductivity-type semiconductor rod having integral first and second portions, the first portion defining a first surface, the second portion defining a second surface opposite the first surface, and a side surface between the first and second surfaces, an active layer and a second conductivity-type semiconductor layer on the side surface of the first conductivity-type semiconductor rod, the active layer and the second conductivity-type semiconductor layer being on the second portion of the first conductivity-type semiconductor rod, an insulating cap layer on the second surface of the first conductivity-type semiconductor rod, a transparent electrode layer on the second conductivity-type semiconductor layer, and a passivation layer on the transparent electrode layer and exposing a portion of the transparent electrode layer, the passivation layer extending to cover ends of the active layer and the second conductivity-type semiType: GrantFiled: September 16, 2020Date of Patent: October 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngjin Choi, Joosung Kim, Jonguk Seo, Sungjin Ahn, Donggun Lee, Jeongwook Lee, Yongseok Choi, Youngjo Tak, Jonghoon Ha
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Patent number: 11784121Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.Type: GrantFiled: March 21, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Kevin L. Lin, Nicholas James Harold McKubre, Richard Farrington Vreeland, Sansaptak Dasgupta
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Patent number: 11784128Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.Type: GrantFiled: June 23, 2021Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Robert Alan May, Kristof Darmawikarta, Sri Ranga Sai Sai Boyapati
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Patent number: 11776869Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.Type: GrantFiled: April 11, 2022Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
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Patent number: 11776968Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.Type: GrantFiled: May 24, 2021Date of Patent: October 3, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
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Patent number: 11776870Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.Type: GrantFiled: January 16, 2020Date of Patent: October 3, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado Tolentino, Shutesh Krishnan, Francis J. Carney
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Patent number: 11769838Abstract: A semiconductor device includes a semiconductor layer, a charge storage layer disposed on the surface of the semiconductor layer via a first insulating film, and an electrode layer disposed on the surface of the charge storage layer via a second insulating film. The charge storage layer includes a first layer containing elemental aluminum and elemental nitrogen, a second layer containing elemental silicon and elemental nitrogen, and a third layer containing elemental oxygen.Type: GrantFiled: April 28, 2022Date of Patent: September 26, 2023Assignee: KIOXIA CORPORATIONInventors: Masaki Noguchi, Akira Takashima, Tatsunori Isogai
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Patent number: 11770925Abstract: A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide.Type: GrantFiled: June 4, 2021Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin A. Kim, Ho-In Ryu, Seong Min Park
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Patent number: 11764125Abstract: A heatsink assembly, a method of producing a heat sink assembly and an electrical device. The heatsink assembly including a heatsink having a surface for receiving a heat source, a copper insert and a layer of low density pyrolytic graphite. The copper insert and the layer of low density pyrolytic graphite are arranged on the surface of the heatsink in layers to form a heat transferring assembly, and the heat transferring assembly is adapted to receive a heat source for transferring the heat from the heat source to the heatsink.Type: GrantFiled: April 14, 2020Date of Patent: September 19, 2023Assignee: ABB Schweiz AGInventors: Jorma Manninen, Mika Silvennoinen, Joni Pakarinen
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Patent number: 11764118Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate, and forming a first adhesive element over the substrate. The first adhesive element has a first electrical resistivity. The method also includes forming a second adhesive element over the substrate. The second adhesive element has a second electrical resistivity, and the second electrical resistivity is greater than the first electrical resistivity. The method further includes attaching a protective lid to the substrate through the first adhesive element and the second adhesive element. The protective lid surrounds the chip structure and covers a top surface of the chip structure.Type: GrantFiled: April 29, 2021Date of Patent: September 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chen-Shien Chen
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Patent number: 11765988Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: GrantFiled: January 7, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Patent number: 11756860Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: July 25, 2019Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon