Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.

Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

Abstract: Examples include a computing system including a heater element for heating a processor device installed in the computing system. The computing system includes a chassis, a circuit board assembly housed in the chassis and a heat sink assembly disposed on the chassis to form a cover of the chassis. The circuit board assembly includes a processor package including a substrate having a first portion and a second portion. The processor package includes the processor device disposed on the first portion of the substrate. The heater element disposed on the second portion of the substrate. In the computing system, the heat sink assembly is disposed on the chassis such that a gap separates the heat sink assembly and the heater element.

Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

Abstract: A power module package structure includes, from top to bottom, a layer of power chips, an upper bonding layer, a thermally-conductive and electrically-insulating composite layer, and a heat dissipation layer. The thermally-conductive and electrically-insulating composite layer contains an insulating layer and an upper copper layer that is formed on the insulating layer. One or more layers of upper packaging materials are covered over the layer of power chips and the upper bonding layer and are in contact with an upper surface of the upper copper layer. One or more layers of lower packaging materials are in contact with the insulating layer and are in contact with sidewalls of the upper copper layer. The lower packaging material has a higher rigidity than the upper packaging material.

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Abstract: A modular distributed control LED display system, comprising several LED display module units (100) which are spliced together to form an integrated LED display screen, each of the LED display module units (100) comprises a lamp board (110) and an independent controller (120), wherein the lamp board (110) is provided with a number of LED light sources, and the independent controller (120) is provided on the back of the lamp board (110), the independent controller (120) is used to control the working state and display mode of the LED light sources.

Abstract: A method for forming an assembly is provided. The method includes depositing a colloidal template onto a substrate, wherein the colloidal template is porous, depositing a metal layer onto and within the colloidal template, depositing a cap structure onto the colloidal template opposite of the substrate, and removing the colloidal template from between the substrate and the cap structure to form a metal inverse opal structure disposed therebetween. The method continues by depositing an electrical isolation layer in contact with the cap structure opposite the metal inverse opal structure, and attaching the electrical isolation layer to a cooling device.

Abstract: An MIM capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a semiconductor substrate, and forming a first metal layer on the semiconductor substrate; forming an anti-reflection layer on the first metal layer; performing photoetching and etching on the first metal layer and the anti-reflection layer so as to define an MIM capacitor region, wherein the first metal layer in the MIM capacitor region serves as a lower electrode plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor; and forming an upper electrode plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region.

Abstract: The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.

Abstract: An IGBT module with a heat dissipation structure having a specific layer thickness ratio includes a layer of IGBT chips, an upper bonding layer, a circuit layer, an insulating layer, and a heat dissipation layer. The insulating layer is disposed on the heat dissipation layer, the circuit layer is disposed on the insulating layer, the upper bonding layer is disposed on the circuit layer, and the layer of IGBT chips is disposed on the upper bonding layer. A thickness of the insulating layer is less than 0.2 mm, a thickness of the circuit layer is between 1.5 mm and 3 mm, and a thickness ratio of the circuit layer to the insulating layer is greater than or equal to 7.5:1.

Abstract: An electronic device, such as, without limitation, a perovskite solar cell or a light emitting diode, includes an assembly including at least one electronic portion or component, and a composite coating layer covering at least part of the assembly including the at least one electronic portion or component. The composite coating layer includes a polymer material, such as, without limitation, PMMA or PMMA-PU, having nanoparticles, such as, without limitation, reduced graphene oxide or SiO2, embedded therein. The electronic device may further include a second coating layer including a second polymer material (such as, without limitation, PMMA or PMMA-PU without nanoparticles) positioned between the coating layer and the assembly.

Abstract: An electronic device includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a plurality of processing components on and/or in the stack, a process control component coupled with at least part of the processing components for transmitting signals and configured for controlling processes executed by the processing components and/or by the process control component, and a heat removal structure on or above which at least one of the process control component and the processing components is arranged.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.