Abstract: A modular distributed control LED display system, comprising several LED display module units (100) which are spliced together to form an integrated LED display screen, each of the LED display module units (100) comprises a lamp board (110) and an independent controller (120), wherein the lamp board (110) is provided with a number of LED light sources, and the independent controller (120) is provided on the back of the lamp board (110), the independent controller (120) is used to control the working state and display mode of the LED light sources.

Abstract: A method for forming an assembly is provided. The method includes depositing a colloidal template onto a substrate, wherein the colloidal template is porous, depositing a metal layer onto and within the colloidal template, depositing a cap structure onto the colloidal template opposite of the substrate, and removing the colloidal template from between the substrate and the cap structure to form a metal inverse opal structure disposed therebetween. The method continues by depositing an electrical isolation layer in contact with the cap structure opposite the metal inverse opal structure, and attaching the electrical isolation layer to a cooling device.

Abstract: An MIM capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a semiconductor substrate, and forming a first metal layer on the semiconductor substrate; forming an anti-reflection layer on the first metal layer; performing photoetching and etching on the first metal layer and the anti-reflection layer so as to define an MIM capacitor region, wherein the first metal layer in the MIM capacitor region serves as a lower electrode plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor; and forming an upper electrode plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region.

Abstract: An IGBT module with a heat dissipation structure having a specific layer thickness ratio includes a layer of IGBT chips, an upper bonding layer, a circuit layer, an insulating layer, and a heat dissipation layer. The insulating layer is disposed on the heat dissipation layer, the circuit layer is disposed on the insulating layer, the upper bonding layer is disposed on the circuit layer, and the layer of IGBT chips is disposed on the upper bonding layer. A thickness of the insulating layer is less than 0.2 mm, a thickness of the circuit layer is between 1.5 mm and 3 mm, and a thickness ratio of the circuit layer to the insulating layer is greater than or equal to 7.5:1.

Abstract: The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.

Abstract: An electronic device, such as, without limitation, a perovskite solar cell or a light emitting diode, includes an assembly including at least one electronic portion or component, and a composite coating layer covering at least part of the assembly including the at least one electronic portion or component. The composite coating layer includes a polymer material, such as, without limitation, PMMA or PMMA-PU, having nanoparticles, such as, without limitation, reduced graphene oxide or SiO2, embedded therein. The electronic device may further include a second coating layer including a second polymer material (such as, without limitation, PMMA or PMMA-PU without nanoparticles) positioned between the coating layer and the assembly.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: An electronic device includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a plurality of processing components on and/or in the stack, a process control component coupled with at least part of the processing components for transmitting signals and configured for controlling processes executed by the processing components and/or by the process control component, and a heat removal structure on or above which at least one of the process control component and the processing components is arranged.

Abstract: A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

Abstract: A wiring substrate of the present disclosure includes a substrate, a first conductive layer, a first insulating layer, and a second conductive layer. The substrate has an insulating surface. The first conductive layer is disposed on the substrate and includes a first part and a second part. The first part has a first thickness. The second part has a second thickness thinner than the first thickness and is adjacent to the first part. The first insulating layer is disposed on the first part and apart from the second part. The first insulating layer is disposed between the second conducting layer and the first part.

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Abstract: An electronic apparatus that includes a semiconductor device; an electronic packaging substrate for receiving the semiconductor device; a thermal interface material on the semiconductor device; and a lid in contact with the thermal interface material and having a zone of targeted flexibility spaced from the semiconductor device.

Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

Abstract: Techniques for controlling top spacer thickness in VFETs are provided. In one aspect, a method of forming a VFET device includes: depositing a dielectric hardmask layer and a fin hardmask(s) on a wafer; patterning the dielectric hardmask layer and the wafer to form a fin(s) and a dielectric cap on the fin(s); forming a bottom source/drain at a base of the fin(s); forming bottom spacers on the bottom source/drain; forming a gate stack alongside the fin(s); burying the fin(s) in a dielectric fill material; selectively removing the fin hardmask(s); recessing the gate stack to form a cavity in the dielectric fill material; depositing a spacer material into the cavity; recessing the spacer material to form top spacers; removing the dielectric cap; and forming a top source/drain at a top of the fin(s). A VFET device is also provided.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

Abstract: A display apparatus includes: a transparent substrate; a panel substrate; a light emitting diode disposed between the transparent substrate and the panel substrate; an insulation layer covering side surfaces of the light emitting diode; a first connection electrode electrically connected to the light emitting diode and disposed on the insulation layer between the insulation layer and the panel substrate; a second connection electrode on the panel substrate; and an electrode connector electrically connecting the first connection electrode to the second connection electrode, wherein the first connection electrode has an overlapping portion overlapping with the light emitting diode and a non-overlapping portion laterally extending from the overlapping portion on the insulation layer.

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Abstract: A monitoring system may include a module configured to couple to a base. The module may include a memory configured to store a firmware application and data, a processor operably coupled to the memory and configured to execute firmware to control the monitoring system, a wireless communication transceiver configured to allow communications between the module and other modules external to the monitoring system, and at least one sensor. The monitoring system is operable to monitor data measured via the at least one sensor and provide monitoring and alarm functions. The module is replaceable separately from the base, which has a shape generally resembling a safety cone.

Abstract: A display apparatus includes a substrate having a display area and a peripheral area, wirings over the peripheral area that extend in a first area to a third area, an interlayer insulating layer covering the wirings and having a first uneven upper surface corresponding to the wirings, a first conductive layer over the interlayer insulating layer and including a second uneven upper surface corresponding to the first uneven upper surface, a planarization layer over the first conductive layer and exposing at least a portion of the first conductive layer, a second conductive layer electrically connected to the first conductive layer, at least a portion of the second conductive layer is over the planarization layer, and a reflection reduction layer on the second conductive layer.

Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.