Patents Examined by Patricia D Valenzuela
  • Patent number: 11404344
    Abstract: A heat spreading plate is suitable to be a top cover of a chip package structure. The heat spreading plate includes a main body and an isolating frame. The main body includes a plurality of metal sheets which are arranged spaced apart from one another totally and capable of thermally connecting different working chips mounted within the chip package structure, respectively. A gap is formed between any two neighboring ones of the metal sheets to completely separate them. The isolating frame surrounds the outer edges of the metal sheets and fills into the gaps for fixedly holding the metal sheets together. One surface of the isolating frame is formed with a plurality of hollow recesses, and each of the metal sheets is exposed outwards from one of the hollow recesses.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Jentech Precision Industrial Co., LTD.
    Inventor: Chun-Ta Yeh
  • Patent number: 11398596
    Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Tanay Gosavi, Ian Young, Dmitri Nikonov
  • Patent number: 11380592
    Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Sridhar Govindaraju, Matthew J. Prince
  • Patent number: 11380770
    Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 5, 2022
    Assignee: Kioxia Corporation
    Inventors: Megumi Ishiduki, Hiroshi Nakaki, Takamasa Ito
  • Patent number: 11367685
    Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Seong-Hyun Kim, Jung-Won Seo, An-Na Choi
  • Patent number: 11362047
    Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 14, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivek Swaminathan Sridharan, Yiqi Tang, Christopher Daniel Manack, Rajen Manicon Murugan, Liang Wan, Hiep Xuan Nguyen
  • Patent number: 11362037
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11362039
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 14, 2022
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Patent number: 11362014
    Abstract: A power module including a circuit board, a chip, a first heat-conduction and insulation substrate and a second heat-conduction and insulation substrate is provided. The circuit board includes a board and a metal block embedded in the board and exposed from a first surface and a second surface of the board opposite to one another. The chip is disposed on a side of the second surface of the board corresponding to the metal block, and the chip is electrically and thermally connected to the metal block. The first heat-conduction and insulation substrate is located on a side of the first surface of the board to be disposed on the circuit board. The second heat-conduction and insulation substrate is electrically and thermally connected to the chip.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 14, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Kai Liu, Yao-Shun Chen, Po-Kai Chiu
  • Patent number: 11358862
    Abstract: A micro-electro-mechanical device, comprising a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region facing the first buried cavity; a second cavity facing the first buried cavity; a decoupling trench extending from the monolithic body and separating the sensitive region from a peripheral portion of the monolithic body; a cap die, forming an ASIC, bonded to and facing the first face of the monolithic body; and a first gap between the cap die and the monolithic body. The device also comprises at least one spacer element between the monolithic body and the cap die; at least one stopper element between the monolithic body and the cap die; and a second gap between the stopper element and one between the monolithic body and the cap die. The second gap is smaller than the first gap.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: June 14, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Enri Duqi, Lorenzo Baldo, Marco Del Sarto, Mikel Azpeitia Urquia
  • Patent number: 11355435
    Abstract: The present application discloses a semiconductor device with air gaps for reducing capacitive coupling between conductive features. The semiconductor device includes a first semiconductor structure including a substrate, a first conductive line positioned above the substrate and including two sides, a first protruding portion positioned on one of the two sides of the first conductive line, a second conductive line positioned adjacent to the first conductive line and including two sides, a second protruding portion positioned on one of the two sides of the second conductive line and face onto the first protruding portion, and an air gap positioned between the first protruding portion and the second protruding portion. A distance between the first protruding portion and the second protruding portion is less than a distance between the first conductive line and the second conductive line.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 7, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chia-Hsiang Hsu
  • Patent number: 11348942
    Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Euntaek Jung, JoongShik Shin, JiHye Yun
  • Patent number: 11348878
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 31, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
  • Patent number: 11348857
    Abstract: A microelectronic device package may include one or more semiconductor dice coupled to a substrate. The microelectronic device package may further include a lid coupled to the substrate, the lid defining a volume over and around the one or more semiconductor die. The microelectronic device package may further include a thermally conductive dielectric filler material substantially filling the volume defined around the semiconductor die.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Xiaopeng Qu
  • Patent number: 11335638
    Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
  • Patent number: 11328978
    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
  • Patent number: 11328992
    Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Richard Farrington Vreeland, Sansaptak Dasgupta
  • Patent number: 11328989
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11328993
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 11322395
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee, Ting-Ya Lo