Abstract: An envelope tracking power amplifier module and an envelope tracking method are provided. The envelope tracking power amplifier module includes a power amplifier and a linear amplifier coupled to the power amplifier and configured to receive and amplify an envelope signal and provide the amplified envelope signal to the power amplifier. The power amplifier is configured to receive and amplify a signal according to the amplified envelope signal. The envelope tracking method includes: providing a signal to the power amplifier; deriving an envelope phase of the signal, the envelope phase corresponding to an output power of the power amplifier; providing an envelope signal including the envelope phase to the envelope tracking module; the envelope tracking module providing the amplified envelope signal to the power amplifier; and the power amplifier amplifying the signal according to the amplified envelope signal and outputting the amplified signal at the output power.

Abstract: Antenna impedance prediction via power amplifier parameter. In some embodiments, a power amplification system can include a splitter circuit and a combiner circuit, and first and second Doherty power amplifiers implemented in a quadrature configuration between the splitter circuit and the combiner circuit, with each Doherty power amplifier including a carrier amplifier and a peaking amplifier. The power amplification system can further include a monitoring circuit configured to measure at least some of base currents associated with the carrier and peaking amplifiers of the first and second Doherty power amplifiers, and generate a signal capable of adjusting a load impedance presented to an output of the combiner circuit.

Abstract: An audio preamplifier includes a first stage including a first triode of a first vacuum tube in a common cathode configuration configured to perform a first gain function favoring one of low frequencies and mid-range frequencies in response to user input; a second stage including a second triode of the first vacuum tube in a common cathode configuration configured to perform a second gain function favoring one of low frequencies and mid-range frequencies in response to user input; a third stage including a first triode of a second vacuum tube in a common cathode configuration configured to perform a tone-shaping function favoring one of low frequencies and mid-range frequencies in response to user input; and a fourth stage including a second triode of the second vacuum tube in a follower configuration configured to perform a tone stack function in response to user input.

Abstract: An automatic gain control circuit of a transimpedance amplifier includes a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS transistor Q1, an NMOS transistor Q2, an error amplifier U3, and a bias current source Ib. An input terminal and an output terminal of the transimpedance amplifier TIA1 are connected to a drain and a source of the NMOS transistor Q1, respectively. An input terminal and an output terminal of the transimpedance amplifier TIA2 are connected to a drain and a source of the NMOS transistor Q2, respectively. An output terminal of the bias current source Ib is connected to a positive input terminal of the error amplifier U3 and the drain of the MOS transistor Q2.

Abstract: High bandwidth envelope trackers are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator that operates in combination with a high bandwidth amplifier to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The high bandwidth amplifier includes an output that generates an output current for adjusting the power amplifier supply voltage, a first input that receives a reference signal, and a second input that receives an envelope signal indicating the envelope of the RF signal. The second input has lower input impedance than the first input to provide a rapid transient response and high envelope tracking bandwidth.

Abstract: An active limiting system that is suitable to protect a low noise amplifier against the high power signals received from a signal input includes, at least one first switch, source of which is connected to a gate voltage; at least first resistor which is connected between the gate and source of the first switch; at least one second resistor, which is connected between a drain voltage and drain of the first switch; at least one second switch, source of which is connected to said drain voltage and drain of which is connected to a signal input; at least one third resistor which is connected between the drain of the first switch and gate of the second switch; at least one first filtering element, which blocks DC currents/voltages and which is connected between the source of the second switch and ground.

Abstract: The disclosure provides an amplifying apparatus including a plurality of amplifying circuits and an adjusting circuit. The input terminals of the amplifying circuits are coupled to a first common node. The output terminals of the amplifying circuits are coupled to a second common node. The adjusting circuit adjusts an input signal to generate an adjusted signal to the first common node; the adjusting circuit adjusts the signal of the second common node; or the adjusting circuit adjusts the input signal to generate the adjusted signal to the first common node and adjusts the signal of the second common node. The first control signal and the second control signal respectively control the amplifying circuits and the adjusting circuit to determine the gain, the linear power, and the output current of the amplifying apparatus.

Abstract: A bias circuit includes a current generating circuit generating a first compensation current and a second compensation current, in which an ambient temperature change is reflected, based on a reference current, a first temperature compensation circuit generating a first base bias current, based on the first compensation current, to output the first base bias current to a base node of an amplifying circuit, and a second temperature compensation circuit generating a second base bias current, based on the second compensation current, to output the second base bias current to the base node of the amplifying circuit.

Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.

Abstract: Various methods and circuital arrangements for protection of a power amplifier from over voltage are presented. According to one aspect, a protection circuit coupled to a varying supply voltage of the power amplifier controls a biasing current to the power amplifier to limit a power dissipation through the power amplifier. An overvoltage protection circuit detects a level of the varying supply voltage and decreases the biasing current as a linear function of an increasing supply voltage once the supply voltage reaches a programmable voltage level. A slope of the linear function can be made programmable. Programmability of the voltage level and the slope can be used to control biasing currents to a plurality of power amplifiers operating at different times and having different requirements in terms of voltage limits and thermal breakdown. According to another aspect a voltage to current converter for use in the overvoltage protection circuit is presented.

Abstract: Modern modulator drivers must be capable of delivering a large output voltage into a tens of ohms modulator, while minimizing the amount of distortion added by the driver. The driver should deliver the output voltage without exceeding a maximum distortion while minimizing the DC power consumption. Accordingly, a modulator driver includes a final stage amplifier with auxiliary transistors that turn on when the conventional differential pair of transistors approaches their maximum voltage of the linear region of their transfer function, thereby providing a more linear transfer function, in particular at large input voltages.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

Abstract: An amplifier circuit comprises a differential input stage configured to receive a differential input signal, wherein the differential input stage is susceptible to an offset error that includes a linear offset error portion and a nonlinear offset error portion; and an offset error correction circuit coupled to the differential input stage and configured to apply a second order error correction signal to the differential input stage to reduce the nonlinear portion of the offset error.

Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor.

Abstract: In some embodiments, a power amplification system can comprise a current source configured to provide a bias current, a current mirror configured to mirror the bias current, a comparator configured to compare the mirrored bias current to a threshold current, and a transistor at an output of the comparator. The transistor can be configured to be activated in response to the mirrored bias current exceeding the threshold current.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.

Abstract: A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.

Abstract: Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.