Abstract: Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.

Abstract: A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

Abstract: A control circuit for a converter for use in a vehicle, such as an electrically powered vehicle. The converter has at least one controllable power semiconductor device. The control circuit is designed to control a changeover procedure of the at least one controllable power semiconductor device based on a control signal, and the control circuit is designed to control the at least one controllable power semiconductor device based on the control signal by temporally adjusting the behaviour of the at least one controllable power semiconductor device during the changeover procedure while taking a shaping parameter into account. The shaping parameter is a shaping parameter for electromagnetic emissions of the at least one controllable power semiconductor device. Also described is a converter for use in a vehicle having the at least one control circuit of that type, a vehicle having at least one converter of that type, and a corresponding method.

Abstract: A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.

Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Abstract: One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes an input circuit, a first control circuit, and an output circuit. The input circuit is configured to receive an input signal and control a level of a first control node according to the input signal and in response to a first clock signal; the first control circuit is configured to control a level of a first node under control of the level of the first control node and the first clock signal; and the output circuit is configured to receive a first voltage of a first voltage terminal and output the first voltage to an output terminal under control of the level of the first node.

Abstract: A shift register unit and a method for driving the same, a gate driver including the same, a display panel and a display device. The shift register unit includes an input terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, an adjustment terminal, an output terminal, a transfer terminal, an input circuit, a first control circuit, and an output circuit. The shift register unit avoids unstableness of the output signal caused by abnormal leakage of charges during the normal output by providing an adjustment signal, and separates the output signal from the transfer signal by means of the output terminal and the transfer terminal, which can reduce the sizes of transistors connected to the output terminal and the transfer terminal, thereby saving the layout area of the shift register unit and decreasing the power consumption thereof at the same time.

Abstract: A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed.

Abstract: This application discloses a shift register, a gate drive circuit and a display device. The signal of the input signal terminal is provided to the pull-up node by the input circuit under the control of the input signal terminal; and the signal of the second reference signal terminal is provided to the output signal terminal by the output circuit under the control of the clock signal terminal and the signal of the pull-up node. The signal of the first reference signal terminal is provided to the pull-up node by the reset circuit under the control of the input signal terminal and the clock signal terminal. The pull-down control circuit resets the output signal terminal according to the signal of the first reference signal terminal.

Abstract: Techniques are described for implementing a true-single-phase-clocking (TSPC) flop with loading functionality. For example, the a loadable TSPC flop can receive input signals, including at least a clock input signal, a SET signal, and a RESET signal. Responsive to one configuration of the input signals, the loadable TSPC flop operates in a normal mode, in which its output node toggles responsive to the clock input signal. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a reset loading mode, such that the Qb output node is loaded and held to a predetermined reset value. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a set loading mode, such that the Qb output node is loaded and held to a predetermined set value that is a complement of the predetermined reset value.

Abstract: A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.

Abstract: A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal.

Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

Abstract: A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the

Abstract: The present disclosure provides to a shift register unit, a driving method, a gate driving circuit, and a display panel. The shift register unit includes: first and second signal terminals respectively outputting high and low levels alternately, a level logic of a signal output from the second signal terminal being opposite to that from the first signal terminal; first and second pull-down control circuits; a first pull-down circuit coupled to the first pull-down node, the first signal terminal, and a pull-down target node, and transmitting, in response to a signal of the first pull-down node, the signal of the first signal terminal to the pull-down target node; a second pull-down circuit coupled to the second pull-down node, the second signal terminal, and the pull-down target node, and transmitting, in response to a signal of the second pull-down node, the signal of the second signal terminal to the pull-down target node.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

Abstract: The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip. The phase locked loop-based power supply circuit includes: a phase locked loop circuit, including a voltage-controlled oscillator (VCO), the phase locked loop circuit outputs, through an output end of the phase locked loop circuit, a control voltage for controlling the VCO; and a voltage regulator, an input end of the voltage regulator is connected with the output end of the phase locked loop circuit, to make the control voltage outputted by the phase locked loop circuit form a power supply voltage after passing through the voltage regulator; the power supply voltage is used for supplying power for a load circuit; the load circuit includes at least one logic gate. The phase locked loop-based power supply circuit reduces timing variations in a digital circuit, and is conducive to implementing timing closure.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.