Abstract: A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data.

Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

Abstract: Disclosed herein are related to systems and methods for providing different power supply levels. In one aspect, a first circuit generates a first signal having a first amplitude according to a first supply voltage. A latch may be coupled to a resistor of a plurality of resistors coupled in series. One end of the resistor may be configured to provide to the latch a second supply voltage higher than the first supply voltage according to a third supply voltage higher than the second supply voltage, and another end of the resistor may be configured to receive the third supply voltage. The latch may modify the first signal to provide a second signal, according to the second supply voltage. An amplifier may amplify the second signal to provide a third signal having a second amplitude larger than the first amplitude, according to the third supply voltage.

Abstract: A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.

Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.

Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.

Abstract: A frequency generator for generating a controlled signal having a controlled frequency uses a frequency ratio generator with an input; a frequency divider for dividing the controlled frequency by a frequency ratio signal to generate a divided signal having a divided frequency; a converter for generating an excitation signal having the divided frequency, the excitation signal exciting a resonator for generating a resonance signal having a resonance frequency; a frequency phase detector of a phase difference between the divided frequency and the resonance frequency; an inner loop filter for generating the frequency ratio signal and filtering the phase difference signal to prevent instability of two frequency ratio generator loops; an output configured for providing the frequency ratio signal based on a ratio between the controlled frequency and the resonance frequency; a controlled oscillator circuit for connecting an oscillator generating an oscillating signal having an oscillator frequency; and a PLL (Phase L

Abstract: A circuit includes a first transistor whose gate is connected to a set terminal and whose source or drain is connected to an internal node, a second transistor connected such that one of a source and a drain is electrically connected to the internal node and the other one of the source and the drain is electrically connected to a reference voltage source, a third transistor connected such that a gate is connected to the internal node, one of a source and a drain is connected to a clock terminal, and the other one of the source and the drain is connected to a first output terminal, a bootstrap capacitor which is connected to the internal node and the first output terminal, and a stabilization circuit that suppresses a drop in potential at the internal node in a charging period of the bootstrap capacitor.

Abstract: Disclosed is a low-pass filtering system having a phase-lock loop comprising a Park transform circuit, a first low-pass filter, a second low-pass filter, an inverse Park transform circuit, a phase-locked loop filter, and a voltage-controlled oscillator. The Park transform circuit, the first low-pass filter, the second low-pass filter, and the inverse Park transform circuit form a phase detector of a phase-locked loop, since the low-pass filter system of the present invention has the phase-locked loop mechanism, the phase and amplitude of a output signal remain the same with those of the original AC input signal.

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract: A windowed watchdog circuit system can include a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold. The windowed watchdog circuit system can include a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorted than the fast threshold. The windowed watchdog circuit system can be configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively.

Abstract: In an embodiment, an electronic circuit includes: a supply management circuit for receiving an input supply voltage and providing a first supply voltage; and a main circuit configured to: when the input supply voltage becomes higher than a first threshold, cause the electronic circuit to transition into an initialization state in which an oscillator is enabled and configuration data is copied from an NVM to configuration registers, and then to transition into a standby state in which the oscillator is disabled and content of the configuration registers is preserved by the first supply voltage, and, upon reception of a wakeup event, cause the configuration data from the configuration registers to be applied to the first circuit, and cause the electronic circuit to transition into an active state in which the first oscillator is enabled and the first circuit is configured to operate based on the configuration data.

Abstract: A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.

Abstract: The present disclosure relates to a dynamic control conversion circuit, which includes: a dynamic control unit configured to generate a dynamic control signal according to a received input signal; a first semiconductor switch, a control terminal of the first semiconductor switch is connected with a first signal output terminal of the dynamic control unit, and a first terminal of the first semiconductor switch is connected with a first voltage terminal; a second semiconductor switch, a control terminal of the second semiconductor switch is connected with a second signal output terminal of the dynamic control unit; and a circuit output unit having a first control terminal connected with a second terminal of the first semiconductor switch and a first terminal of the second semiconductor switch, and a second control terminal connected with a second terminal of the second semiconductor switch and a third signal output terminal of the dynamic control unit.

Abstract: A closed loop switch control system and a corresponding method is provided for controlling an impedance of a switch. The switch, which usually comprises a transistor switch, may be part of an external circuit. The system comprises the switch and a control unit coupled to the switch. The control unit is configured to regulate an impedance of the switch to a reference impedance while also enabling a fast switch response time. This is achieved by configuring the control unit to have a frequency response comprising a plurality of dominant poles and at least one zero.

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

Abstract: A serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer and a plurality of flip-flops coupled to the multiplexer. Each serializer unit cell contains a state machine defining operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.