Abstract: A data processing device has load and store instructions which address memory with the content of a data pointer register. In a normal mode, the same data pointer register is used for all load and store instructions. In this mode the processor is compatible with a older processor design. In a special mode, at least two different registers are used alternately to address memory when memory access instructions are executed. A control register controls whether or not the different registers are updated as part of the memory access instructions. Preferably, the control register provides for more than one different kind of update of the different registers, such as post addressing increment, post addressing decrement etc.

Abstract: Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.

Abstract: A method, system, and computer program product to enable a user to specify an intended use for a logical volume. The logical volume is configured using an application-specific template (also referred to as a user template) for an application, where the application-specific template satisfies the intended use. Rules from the application-specific template are stored with the logical volume in addition to or as part of the intent.

Abstract: In a storage apparatus system, after having obtained the coherency between a file system of a main storage apparatus system and the stored data, a host computer issues a freezing instruction to a main DKC which transfers in turn the disk image at a time point of the issue of freezing instruction to a sub-DKC and then transmits a signal, showing that all the data has been transmitted, to the sub-DKC. In the sub-DKC, the disk image at a time point of reception of the freezing instruction is held until a signal showing that all the data has been transmitted is issued next time, and when the main storage apparatus system becomes unusable at an arbitrary time point, the data of the disk image, at a time point of issue of the freezing instruction, which is held by the sub-storage apparatus system can be utilized.

Abstract: A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.

Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.

Abstract: This invention provides a control technique of a data processing system, in which functions of a highly-functional high-performance storage system are achieved in an inexpensive storage system so as to effectively use the existing system and reduce the cost of its entire system. This system has a RAID system, an external subsystem, a management server, a management client and the like. The management server includes an information management table for storing mapping information of the RAID system and the external subsystem. When performing copy process, the pair creation in which a logical volume of the RAID system is set as a primary volume of copy source and a logical volume of a mapping object of the RAID system mapped from the logical volume of the external subsystem is set as a secondary volume of copy destination is executed from the management client by using the information management table.

Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.

Abstract: The present invention aims at providing a semiconductor memory device that can be operational in a desired boot block mode, regardless of the original boot block type of the device, by facilitating rewriting of the memory device. A sector address from an outside source is inputted into a sector-address conversion circuit, which converts the sector address into an internal address, and a memory cell array is accessed through an address decoder circuit. Suppose that each of banks of the memory device is configured as a bottom boot type. By converting the sector address by the sector-address conversion circuit such that the sector-address now appears to the outside in the reverse order, each of the banks now functions as a top boot type.

Abstract: A memory structure and method for handling memory requests from a processor and for returning correspondence responses to the processor from various levels of the memory structure. The memory levels of the memory structure are interconnected by a forward and return path with the return path having twice the bandwidth of the forward path. An algorithm is used to determine how many responses are sent from each memory level on the return path to the processor. This algorithm is designed to guarantee a constant bound on the rate of responses sent to the processor. More specifically, if a write request is at the same level to which it is targeted, or if a request at a memory level is targeted to a higher memory level, then two responses are forwarded from a controller at the memory level on the return path to the processor. Otherwise, only one response is forwarded from the memory level on the return path.

Abstract: Described are a system and method of accessing vital product data (VPD) information. A first processing system may initiate a configuration write request to a VPD address register. A second processing system may access a VPD data register associated with the VPD address register in response to an interrupt signal.

Abstract: A method and system for efficient coalescing of memory blocks across memory heap boundaries in multiprocessor or multithread computer system. Blocks of memory are allocated into multiple heaps for exclusive utilization by separate processors or processes. Varying memory requirements result in fragmentation and increased memory utilization over time and coalescing of memory is necessary. An identification of each memory heap which contains a preceding adjacent memory block and a succeeding adjacent memory block is maintained for all memory blocks. Thereafter, each time a memory block is freed it may be coalesced across heap boundaries with an adjacent preceding or succeeding memory block by temporarily locking access to only those memory heaps containing a free preceding or succeeding adjacent memory block.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

Abstract: A system and method for updating electronic files and file components are provided. An upgrade client of a remote device receives a delta file block that codes differences between an original and a new version of a file. The upgrade client stores the delta file block in a first memory area. The upgrade client writes an original file block corresponding to the delta file block from an original memory area to a second memory area. A file updating algorithm generates an updated file block in the host device using the received delta file block and the original file block. This updated file block corresponds to the original file block, and is stored in a third memory area. The upgrade client updates the original file block of the remote device by writing the updated file block over the original file block in the original memory area of the remote device.

Abstract: In one embodiment of the method, first and second data volumes are created. Thereafter, a first data portion of the first data volume is overwritten with a first data portion of the second data volume. A second data portion of the first data volume is overwritten with a second data portion of the second data volume. In one embodiment, the first and second data portions of the first data volume are overwritten with the first and second data portions of the second data volume, respectively, in response to a command to restore or synchronize the data contents of the first data volume to the data contents of the second data volume. A virtual point-in-time (PIT) copy of the first data volume is created after overwriting the first data portion but before overwriting the second data portion.

Abstract: A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache directory, one or more processing units, and a memory coherent directory to keep track of the scope of ownership of data within the modular multiprocessing computer system. The local memory and the local cache contain configurable regions of storage, wherein memory coherency traffic on the communication links between the nodes is controlled through the use of the memory coherent directory during a data request.

Abstract: Two data centers located in the vicinity are connected using a synchronous transfer copy function, and one of the data centers is coupled with a third data center disposed at a remote location by an asynchronous remote copying function. The order whereat a storage sub-system located in the vicinity has received data from a host is consistently guaranteed, and the third data center holds the data. Further, each storage sub-system includes a function whereby, during normal operation, data can be exchanged and the data update state can be obtained by the storage sub-systems located in the two data centers that do not directly engage in data transmission.

Abstract: A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count.

Abstract: A method, system, and program for fast paging of a large memory block are provided. A request to physically remove a memory block device from a data processing system is received. A logical volume within disk space is dynamically allocated for a contiguous paging space. Multiple logical pages for the memory block devices are translated into multiple physical addresses for the memory block device. A single input/output request is issued to page out data located at the multiple physical addresses to the contiguous paging space, such that after the single request is complete, the memory block device can be safely removed. Further, when a replacement memory block device is detected, a single input/output request is issued to page in data located within the contiguous paging space to the replacement memory block.

Abstract: A method and apparatus for a multi-channel high speed framer is described. In one embodiment, the invention is an apparatus. The apparatus includes a first plurality of pipeline stages suitable for data framing between a link layer and a network interface. The apparatus also includes a first memory coupled to each pipeline stage of the first plurality of pipeline stages, the first memory to store context information at predetermined stage locations for each pipeline stage. The apparatus further includes a first control logic coupled to the first memory and to each pipeline stage of the first plurality of pipeline stages, the first control logic to control transfer of data between the first memory and the first plurality of pipeline stages. Within the apparatus, each stage of the first plurality of pipeline stages is suitable for loading the context information from the first memory through first control logic and performing a sub-function of data framing.