Abstract: A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Abstract: A method for processing requests or commands for writing and reading to and from memory that has not been allocated and reserved for one or more volumes, and a method for establishing one or more volumes, where the one or more volumes define an area of the memory that is accumulatively greater than the actual memory capacity, thus allowing for memory to be added at a later time.

Abstract: A method for a byte swap operation on a 64 bit operand. The method of one embodiment comprises accessing an operand stored in a register. The operand is comprised of a plurality of bytes of data. A first set of bytes located in an upper half of said register is reordered. A second set of bytes located in a lower half of said register is reordered. The first set of bytes is swapped with the second set of bytes, wherein the first set of bytes is relocated to the lower half of the register and the second set of bytes is relocated to the upper half of the register.

Abstract: Storage services and systems are provided. Virtual disks include a number of storage states and are associated with storage operations that are provided with the virtual disks. Moreover, a storage management set of executable instructions is configured based on values assigned to the states when the storage operations are performed against the virtual disks. In some embodiments, a selection set of executable instructions permits the selective execution of the storage operations.

Abstract: A method of determining an order of execution of a plurality of queued commands in a data storage system includes the step of determining a execution path metrics for each of a plurality of commands in a waiting queue. Each execution path metrics is determined both as a function of an access time between a last command in a ready queue and the associated command in the waiting queue, and as a function of an access time between the associated one of the commands in the waiting queue and another of the commands in the waiting queue. Based upon the determined execution path metrics, one of the commands in the waiting queue is selected and moved from the waiting queue to the ready queue. Also disclosed is a data storage system configured to implement the method.

Abstract: A method and a search engine are described. A unique key is received. A hash is searched for a match to the unique key. Concurrently with searching the hash, a cache is searched for the match to the unique key. And information regarding the unique key is obtained.

Abstract: A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split according to the interleaved cache and interleaving of the cache directory is independent of address bits used for cache interleaving.

Abstract: Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an array including a number of elements each including an address. The first element of the array includes an address less than the address of every other element of the array. The logic accesses a base-pointer offset, adds the base-pointer offset to the base pointer to calculate an address of a current element of the array, and stores the calculated address for subsequent access by one or more operations. After the current element has been accessed by the one or more operations, the logic increments the base-pointer offset by one, accesses a maximum offset value equal to the number of elements of the array, and compares the incremented base-pointer offset with the maximum offset value. If the incremented base-point offset is less than the maximum offset value, the logic stores the incremented base-pointer offset.

Abstract: A file management method, whereby inconsistencies can be prevented between a file recorded in a memory card and the file management information that a terminal apparatus manages, without leaking the information of a file made and stored in an in-card processing system. According to this method, a flash memory accessible from two processing systems 100 and 300 is provided. First processing system 100 requests a reservation of an use area of flash memory 200a to second processing system 300, which, upon receiving the request, implements a reservation processing for an area of the memory section and reflects the information of the reserve area upon file management section 230. First processing system 100 performs the processing of writing data into the area reserved by second processing system 300. Inconsistencies between the file management information that a terminal manages and a file actually recorded into the memory section of a secure card can be prevented.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Abstract: The disclosed system and method describe a ternary CAM device having, in addition to a data entry and a ternary mask entry, one or more additional control words which can specify a net mask length and status, a table identifier, and/or a validity word to specify a detailed status of the segmented data words stored. This allows for the matching of ternary CAM device entries with a comparand without sorting ternary CAM device entries. Additional status words can be used for table identification to save space in the actual data word entries, and also allowing for matching of data entries with selected table identifiers, precluding having to search the entire ternary CAM array. Additional status words can also be used to provide additional state information to provide more flexibility in validity checking. The disclosed system and method can be used in ternary CAM devices having and/or supporting varying word widths.

Abstract: A multimedia file has a format in which actual data is embedded in a file structure. The multimedia information is assembled in blocks, each composed of a header area and a data area, and has a hierarchical structure in which a block is embedded in another block. Header area information may include a file name identification information (block name), a number of child blocks information and data length identification information. This arrangement facilitates the creation and editing of a multimedia file, permitting high-speed data searching.

Abstract: An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same doubleword detection unit receives a first instruction including a plurality of first instruction fields on a first pipe and a second instruction including a plurality of second instruction fields on a second pipe. The same doubleword detection unit generates a same doubleword signal in response to the first instruction fields and the second instruction fields. The cache storage reads data from a single doubleword in the cache storage and simultaneously provides the doubleword to the first pipe and the second pipe in response to the same doubleword signal.

Abstract: A method for conducting checkpointing within a writeback cache having a cache memory with at least two memory banks. In one embodiment, a first pointer is set to indicate which cache entry of the at least two memory banks contains current data. A second pointer is set to indicate which cache entry of the at least two memory banks contains checkpoint data. Checkpointing is performed by selectively controlling said second pointer or said first pointer.

Abstract: A multiprocessor system and method includes a processing sub-system having a plurality of processors and a processor memory system. A scalable network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces. Each I/O interface has a local cache and is operable to couple a peripheral device to the multiprocessor system and to store copies of data from the processor memory system in the local cache for use by the peripheral device. A coherence domain for the multiprocessor system includes the processors and processor memory system of the processing sub-system and the local caches of the I/O sub-system.

Abstract: In one embodiment of the method, first and second data volumes are created. Thereafter, a first data portion of the first data volume is overwritten with a first data portion of the second data volume. A second data portion of the first data volume is overwritten with a second data portion of the second data volume. In one embodiment, the first and second data portions of the first data volume are overwritten with the first and second data portions of the second data volume, respectively, in response to a command to restore or synchronize the data contents of the first data volume to the data contents of the second data volume. A virtual point-in-time (PIT) copy of the first data volume is created after overwriting the first data portion but before overwriting the second data portion.

Abstract: A method and apparatus that moves data stored in a first (e.g., 512) byte sector format to a second (e.g., 52x) byte sector size. The method and apparatus performs data migration without interruption of the host's ability to write and read data from the system. By migrating data to a number of new drives added to the system drive, the additional data which will be stored may be accommodated. The added drives allow the migration to take place without interruption of the hosts I/O path or allows the data to be migrated to an entirely new set of physical drives. The present invention also provides the ability to migrate data between sector sizes and still protect against component failures. The migration is performed in such a way that if a controller fails while performing the migration the survivor controller will be able to pick up where the failed controller left off.

Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

Abstract: This invention describes methods, apparatus and systems for virtualization of iSCSI storage. Virtual storage isolates the clients from the management of physical storage resources. In this invention, each physical storage device supports multiple logical units (LUNs). Each supported LUN is associated with a separate TCP port number and iSCSI commands received on a given port implicitly refer to the associated LUN. An iSCSI host addresses each logical unit of storage (LUN) with a virtual IP address and port number. Using an address translation table, the virtualization gateway rewrites the destination IP address in the header of an incoming packet as well as the destination port number to correspond to the target physical LUN. Migration of logical units across physical storage devices is supported by changing the address translation entries at the gateway; and the gateway can be provided by a standard network router with support for address translation.

Abstract: A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.