Abstract: A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.

Abstract: A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.

Abstract: A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.

Abstract: A method of reading data on a disk drive suited to an operating system that does not support the disk drive. First, the system allocates a free memory space in a memory thereof. Then the system reads the data in all the sectors of the disk with a reading routine, and saves the data in the free memory space. While receiving a disk drive reading command, the system processes the data saved in the free memory space according to the disk drive reading command. Thus, the drawback of the repeatedly turning on and off the disk drive is avoided while reading data with a length larger than a sector.

Abstract: A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.

Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

Abstract: The present invention provides a method, system, and computer program product for selectively replacing cached content (including, but not limited to, dynamically generated Web pages which have been cached) to provide a higher level of service to particular users or groups of users. Service providers may use the disclosed techniques to justify charging for an enhanced quality of service. The disclosed techniques enable reducing, in many cases, the system overhead and response time required for delivering content to those content requesters who have this type of enhanced service. When content is evaluated for potential caching and the cache is determined to be full, content is selected for overwriting according to the quality of service level of the content owner.

Abstract: This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be writeback of data cached from the program designated address range to a higher level memory or such writeback and invalidation of data cached from the program designated address range. A cache operation unit includes a base address register and a word count register loadable by the central processing unit. The program designated address range is from a base address for a number of words of the word count register. In the preferred embodiment the program controlled cache state operation begins upon loading the word count register. The cache operation unit may operate on fractional cache entries by handling misaligned first and last cycles. Alternatively, The cache operation unit may operate only on whole cache entries. The base address register increments and the word count register decrements until when the word count reaches zero.

Abstract: A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes at least one entry for translating a group of non-physical addresses to physical addresses that individually specifies control information pertaining to the group of non-physical addresses for each of the plurality of nodes. The control information may include one or more data storage control fields, which may include a plurality of write through indicators that are each associated with a respective one of the plurality of nodes. When a write through indicator is set, processing units in the associated node write modified data back to system memory in a home node rather than caching the data.

Abstract: A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, and a memory controller coupled to the local interconnect and the home system memory. In response to receipt of a data request from the remote node, the memory controller transmits requested data from the home system memory to the remote node and, in a separate transfer, conveys responsibility for global coherency management for the requested data from the home node to the remote node. By decoupling responsibility for global coherency management from delivery of the requested data in this manner, the memory controller queue allocated to the data request can be deallocated earlier, thus improving performance.

Abstract: A data storage system randomly determines a start offset at which to write objects to a storage medium. For updated blocks of the object, e.g., for blocks written during copy-on-write as part of a point-in-time snapshot, the updated block is written in the region of the original file or as close thereto as possible to achieve “virtual contiguity”. Subsequent reads of the object read entire region containing both the object and, potentially, “chaff” data other than the object. The “chaff” data is discarded by the I/O system or file system using, e.g., a bit mask, subsequent to the read.

Abstract: A hot-pluggable memory cartridge for use in a redundant memory system. More specifically, the control logic and method for implementing a plurality of memory cartridges which may be hot-plugged into a memory sub-system.

Abstract: A system for adaptively bypassing one or more higher cache levels following a miss in a lower level of a cache hierarchy is described. Each cache level preferably includes a tag store containing address and state information for each cache line resident in the respective cache. When an invalidate request is received at a given cache hierarchy, each cache level is searched for the address specified by the invalidate request. When an address match is detected, the state of the respective cache line is changed to the invalid state, although the address of the cache line is left in the tag store. Thereafter, if the processor or entity associated with this cache hierarchy issues its own request for this same cache line, the cache hierarchy begins searching the tag store of each level starting with the lowest cache level.

Abstract: The present invention increase the efficiency of virtual memory usage when performing heap allocation and reduces virtual memory fragmentation caused by heap allocation. Instead of incrementally growing the initial heaps when there is not enough heap memory to make an allocation, an entirely new heap is created in which to make the allocation. That new heap may be added to the pool of heaps from which an allocation may be made. The additional heaps are of a constant, relatively large, size thereby reducing the risk of virtual memory fragmentation.

Abstract: In a storage apparatus system, after having obtained the coherency between a file system of a main storage apparatus system and the stored data, a host computer issues a freezing instruction to a main DKC which transfers in turn the disk image at a time point of the issue of freezing instruction to a sub-DKC and then transmits a signal, showing that all the data has been transmitted, to the sub-DKC. In the sub-DKC, the disk image at a time point of reception of the freezing instruction is held until a signal showing that all the data has been transmitted is issued next time, and when the main storage apparatus system becomes unusable at an arbitrary time point, the data of the disk image, at a time point of issue of the freezing instruction, which is held by the sub-storage apparatus system can be utilized.

Abstract: The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect to which a remote node and a home node are coupled. The home node contains a home system memory, and the remote node includes at least one processing unit and a cache. In response to the cache deallocating an unmodified cache line that corresponds to data resident in the home system memory, a cache controller of the cache issues a deallocate operation on a local interconnect of the remote node. In one embodiment, the deallocate operation is further transmitted to the home node via the node interconnect only in response to an indication, such as a combined response, that no other cache in the remote node caches the cache line. In response to receipt of the deallocate operation, a memory controller in the home node updates a local memory directory associated with the home system memory to indicate that the remote node does not hold a copy of the cache line.

Abstract: A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and shared memory. Bus snooping capabilities are enabled by a stand-alone bus snooping device connected to the bus and the caching device or by bus snooping functions incorporated into the caching device. The bus snooping device monitors communications on the bus and causes invalidation of cached information to maintain cache coherency before the communications complete.

Abstract: An apparatus a communication bridge which receives a portion of data from at least one source terminal, assigns a data identifier to the data, and causes the data and data identifier to be stored to a tape storage device for subsequent access is disclosed.

Abstract: A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote node includes a local interconnect, a processing unit and at least one cache coupled to the local interconnect, and a node controller coupled between the local interconnect and the node interconnect. The processing unit first issues, on the local interconnect, a read-type request targeting data resident in the home system memory with a flag in the read-type request set to a first state to indicate only local servicing of the read-type request. In response to inability to service the read-type request locally in the remote node, the processing unit reissues the read-type request with the flag set to a second state to instruct the node controller to transmit the read-type request to the home node.