Patents Examined by Paul E Patton
  • Patent number: 8574940
    Abstract: A flexible optoelectronic device having inverted electrode structure is disclosed. The flexible optoelectronic device having inverted electrode structure includes a flexible plastic substrate having a cathode structure, an n-type oxide semiconductor layer, an organic layer, and an anode. The n-type oxide semiconductor layer is disposed on the cathode structure. The organic layer is disposed on the n-type oxide semiconductor layer. The anode is electrically connected with the organic layer.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 5, 2013
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Kao-Hua Tsai
  • Patent number: 8048780
    Abstract: A method of dividing an optical device wafer includes: a laser beam processing step of performing laser beam processing on the face side of an optical device wafer so as to form breakage starting points along streets; a protective plate bonding step of bonding the face side of the optical device wafer to a surface of a highly rigid protective plate with a bonding agent permitting peeling; a back side grinding step of grinding the back side of the optical device wafer so as to form the optical device wafer to a finished thickness of optical devices; a dicing tape adhering step of adhering the back-side surface of the optical device wafer to a dicing tape; a cut groove forming step of cutting the protective plate bonded to the optical device wafer along the streets so as to form cut grooves; and a wafer dividing step of exerting an external force on the optical device wafer through the protective plate, so as to break up the optical device wafer along the breakage starting points formed along the streets, there
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 1, 2011
    Assignee: Disco Corporation
    Inventors: Hitoshi Hoshino, Takashi Yamaguchi
  • Patent number: 8044475
    Abstract: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 25, 2011
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo
  • Patent number: 8030765
    Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: October 4, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 8030151
    Abstract: A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1 or 267-2) is provided above the base link portion. The length of the base link portion is determined, and thereby controlled, with a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, provided on the dielectric layer above the base link portion. The lateral spacing portion is typically provided as part of a layer of non-monocrystalline semiconductor material used in the gate electrode of an insulated-gate field-effect transistor.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: October 4, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeng-Jiun Yang, Constantin Bulucea
  • Patent number: 8026610
    Abstract: A method for manufacturing a silicon interposer, includes a step of forming a protection film on a surface, on which an element portion is formed, of a silicon wafer, a step of forming open holes according to planar arrangements of through holes which pass through the silicon wafer in a thickness direction, a step of forming the through holes by etching the silicon wafer using the protection film as a mask, a step of forming an oxide film on inner wall surfaces of the through holes by a thermal oxidation, a step of forming a contact hole, which is in communication with the element portion, in the protection film, and a step of forming wirings on both surfaces of the silicon wafer. In the step of forming the wirings, one of the wirings is formed to be connected electrically to the element portion via a contact portion formed in the contact hole.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: September 27, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kei Murayama
  • Patent number: 8022521
    Abstract: In accordance with one embodiment, a failure prognostic package includes a substrate having a first surface and an opposite second surface. An electronic component trace is coupled to the first surface. An electronic component is electrically coupled to the electronic component trace. A prognostic trace is coupled to the first surface of the substrate and is electrically isolated from the electronic component. A failure zone of the failure prognostic package includes a plurality of sides and a plurality of corners, wherein the prognostic trace is weaker at the failure zone than the electronic component trace. Failure of the prognostic trace does not cause failure of the failure prognostic package. However, failure of the prognostic trace provides advanced notice of failure of the failure prognostic package.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: September 20, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Akito Yoshida, Mahmoud Dreiza
  • Patent number: 8022460
    Abstract: An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Patent number: 8021932
    Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada
  • Patent number: 8022511
    Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: September 20, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung Chiu, Chih-Pin Hung, Jui-Cheng Huang
  • Patent number: 8013849
    Abstract: An active-matrix device includes a substrate; a plurality of pixel electrodes provided on a first surface of the substrate; a plurality of switching elements provided to correspond to each of the pixel electrodes, each of the switching elements including a fixed electrode connected to the each pixel electrode, a movable electrode mainly made of silicon and displaceably provided so as to contact with and separate from the fixed electrode, and a driving electrode provided to oppose the movable electrode via an electrostatic gap; a first wiring connected to the movable electrode; and a second wiring connected to the driving electrode, wherein a voltage is applied between the movable electrode and the driving electrode to generate an electrostatic attraction between the movable electrode and the driving electrode so as to displace the movable electrode such that the movable electrode contacts with the fixed electrode to electrically connect the first wiring to the pixel electrode.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: September 6, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Isamu Namose
  • Patent number: 8008664
    Abstract: An electrical component, in the crystalline semiconductor body of which several CMOS transistors in high-voltage or low-voltage technology are formed. The individual CMOS transistors are separated from one another by insulation regions. On one insulation region, a thin-film transistor is formed, having a gate that is realized simultaneously with the gates of the CMOS transistors from the same polysilicon layer. The gate oxide of the thin-film transistor, just like a second polysilicon layer for source drain and body of the thin-film transistor, can be produced together with the structural elements already present in the CMOS process.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: August 30, 2011
    Assignee: austriamicrosystms AG
    Inventor: Hubert Enichlmair
  • Patent number: 8004029
    Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama
  • Patent number: 7998819
    Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: August 16, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Bruce D. Marchant, Dean Probst
  • Patent number: 7999382
    Abstract: A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of the grooves; a first interconnect part and a first bonding electrode part including a copper film formed on the first barrier metal; a second barrier metal formed on the first interconnect part and the first bonding electrode part; a second interconnect part including a metal film formed on the first interconnect part via the second barrier metal; a second bonding electrode part including a metal film formed on the first bonding electrode part via the second barrier metal; and a third interlayer insulating film formed on the second interlayer insulating film, the second interconnect part, and the second bonding electrode part, and including an opening that allows exposure of the surface of the second bonding electrode part.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaki Yamada
  • Patent number: 7989920
    Abstract: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: August 2, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzyh-Cheang Lee, Ming-Yi Yang, Fu-Liang Yang, Denny Duan-Iee Tang
  • Patent number: 7989952
    Abstract: A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 7989332
    Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Yasuhiro Jinbo, Satoshi Kobayashi, Daisuke Kawae
  • Patent number: 7985966
    Abstract: An electro-optically active organic diode, for example an organic light emitting diode (OLED), comprises an anode electrode (102), a cathode electrode (122) and an electro-optically active organic layer (110) arranged in-between. A cover layer (124) is arranged in contact with a surface of the cathode layer (122) so that the cathode layer (122) is positioned between the organic layer (110) and the cover layer (124), which is formed of a substantially inert material with respect to a cathode layer (122) material in contact with said cover layer (124). The inert material is deposited on said surface of the cathode layer (122) so that the complete surface is covered and surface defects eliminated. A short protection layer (120) is further arranged between said cathode electrode (122) and said electro-optically active organic layer (110), and adjacent to said cathode electrode (122), and is formed of an inorganic semiconductor material.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: July 26, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Michael Buechel, Edward Willem Albert Young
  • Patent number: 7986030
    Abstract: A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: July 26, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventor: Takeshi Meguro