Abstract: The present invention relates to a COG-typed organic electroluminescent device including dummy data lines formed at different location from data lines. The COG-typed organic electroluminescent cell having a plurality of pixels formed in the luminescent areas which are cross areas of indium tin oxide films (ITO films) and metal line layers includes data line pads, dummy data lines, and a dummy data line connecting section. The data line pads each are connected to one end of the ITO films. The dummy data lines each are connected to the other end of the ITO films. The dummy data line connecting section connects the dummy data lines. In the cell, the dummy lines are formed separately from the pads, and thus the number of pins may be reduced.

Abstract: A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact area. A recess gate is formed in the gate area of the semiconductor substrate including the first groove. A first junction area is formed in the storage node contact area of the semiconductor substrate. A second junction area is formed in the bit line contact area of the semiconductor substrate under the second groove.

Abstract: An illumination module with at least one thin-film light emitting diode chip which is applied on a chip carrier having electrical connecting conductors and has a first and a second electrical connection side and also an fabricated semiconductor layer sequence. The semiconductor layer sequence has an n-conducting semiconductor layer, a p-conducting semiconductor layer and an electromagnetic radiation generating region arranged between these two semiconductor layers and is arranged on a carrier. Moreover, it has a reflective layer at a main area facing toward the carrier, which reflective layer reflects at least one part of the electromagnetic radiation generated in the semiconductor layer sequence back into the latter. The semiconductor layer sequence has at least one semiconductor layer with at least one micropatterned, rough area.

Abstract: A semiconductor device comprises a package having a cavity in the interior thereof, a chip having a semiconductor element, and an adhesive portion comprised of a silicone or fluorine resin and particles each having a predetermined shape. The adhesive portion fixes the chip on the bottom of the cavity.

Abstract: A connecting structure between a circuit and another electronic component, includes a first electrode and a second electrode, and a dielectric material interposed between the first and second electrodes.

Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: The CMP technology is provided for a damascene wiring structure having a plural-layer wiring that is excellent in flatness and resolvability of Cu residue. An evaluation substrate is provided for evaluating the condition of a CMP that is employed for configuring a semiconductor device having a plurality of wirings in a vertical direction, and the evaluation substrate comprises: a substrate; a first groove formed on the substrate; a second groove formed on the substrate; and wiring material provided in the first groove and the second groove, wherein a depth of the second groove is shallower than that of the first groove.

Abstract: A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

Abstract: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.

Abstract: A semiconductor device having macro circuit including concentrated fine interconnections and extension wiring for connecting the macro circuit and the outer circuit. The widths of the fine interconnections are less than 0.1 ?m. An end of the extension wiring is connected to at least two of fine interconnections of the macro circuit arranged in parallel. By this configuration, the possibility of disconnection at the portion where the end of the extension wiring and the fine interconnections are connected is suppressed.

Abstract: This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

Abstract: A semiconductor light emitting device includes: a body having a recess, a step being provided on a side wall of the recess; a semiconductor light emitting element mounted in the recess; and a resin layer. The resin layer covers at least a portion of an inner surface of the recess of the body. The resin layer has a higher reflectivity than the inner surface of the recess of the body.

Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

Abstract: The object of the present invention is to provide a light-emitting element mounting member and a semiconductor device using the same that is easy to process and that allows adequate heat dissipation. A light-emitting element mounting member 200 includes: a substrate 2 including an element mounting surface 2a mounting a semiconductor light-emitting element 1 and first and second conductive regions 21, 22 disposed on the element mounting surface 2a and connected to the semiconductor light-emitting element 1; a reflective member 6 including a reflective surface 6a defining an internal space 6b for housing the semiconductor light-emitting element 1 and containing a metal disposed on the element mounting surface 1a; and a metal layer 13 disposed on the reflective surface 6a. The reflective surface 6a is sloped relative to the element mounting surface 2a so that a diameter of the internal space 6b is greater away from the element mounting surface 2a.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: A semiconductor device includes a solder dam for restricting the flow of solder during manufacturing. The device includes a semiconductor chip bonded to a first side of a circuit board, a metal base for dissipating heat produced by the semiconductor chip, the metal base being bonded to a second side of the circuit board, and a dam material disposed on the metal base in a predetermined pattern for restricting the flow of solder used in bonding a plurality of the circuit boards to the metal base. By employing the solder dam, solderability is not impaired, device contamination can be avoided, and a highly reliable semiconductor device can be produced.

Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.

Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.

Abstract: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor of blue pixels can be made larger than that of the red or green pixels. In another aspect of the invention, depicted in the exemplary embodiments, the honeycomb structure can also be implemented with each pixel row having a same color of pixel cells which can simplify can conversion in the readout circuits. In another aspect of the invention, the RGB honeycomb pixel array may be implemented using a shared pixel cell architecture.

Abstract: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.