Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block, a second block and a third block. The first block includes a plurality of initial-address-unit groups and each initial-address-unit group includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable. The second block includes a plurality of initial address control units and each initial address control unit corresponds to one of the variables to record the corresponding initial-address-unit group of each variable. The third block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is configured to assign the storage addresses to the variables.

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion, a tag memory portion, and one or more peripheral circuits configured to receive a CPU address corresponding with an address of the RAM memory storing a particular CPU instruction. The one or more peripheral circuits are configured to receive a way quantity indication indicating of a number of ways into which the instruction memory portion and the tag memory portion are to be subdivided, the one or more peripheral circuits are configured to identify which bits of the CPU address form the tag portion based on the way quantity indication, and the one or more peripheral circuits are configured to determine whether the particular CPU instruction is stored in the cache memory based on the identified tag portion of the CPU address and tag data stored in the cache memory.

Abstract: A method for monitoring memory access behavior of a sample process is provided. A processing unit of a computer device determines a page table of the sample process based on a page directory base address of the sample process, where each entry of the page table includes first information, the first information indicates whether the entry has been assigned a guest physical address, the entry that has been assigned the guest physical address includes second information that is used to indicate an access permission of the assigned guest physical address; determines a target entry from the page table, the target entry has been assigned a guest physical address, and an access permission is execution allowed; determines a target host physical address corresponding to the target guest physical address that is assigned to the target entry; and monitors behavior of accessing memory space indicated by the target host physical address.

Abstract: A recording control apparatus that records data on a recording medium includes a position recording unit configured to perform control so that, upon completion of recording of data, a recording start position for next recording of data is recorded on the recording medium, an initialization unit configured to initialize the recording medium, and a control unit configured to perform control in such a manner that in a case where the initialization unit executes first initialization processing, the first initialization processing and clear processing for clearing the recording start position recorded on the recording medium are executed, and in a case where the initialization unit executes second initialization processing, the second initialization processing is executed without executing the clear processing.

Abstract: An information management system is described herein that performs either a pre-processing or a post-processing operation to increase browse and restore speeds when a user attempts to browse for and restore files from a secondary copy of a data volume. For example, the information management system can implement the pre-processing operation by parsing a master file table (MFT) when a secondary copy operation is initiated on the data volume. The information management system can implement the post-processing operation by parsing the MFT after a secondary copy operation is complete. The parsing can occur to identify records of the MFT that include information useful for enabling a user to browse a secondary copy of the data volume. The information management system can then store the secondary copy of these records for use later in constructing an interface for browsing a secondary copy of the data volume.

Abstract: Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

Abstract: An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.

Abstract: Techniques related to automatic cache management are disclosed. In some embodiments, one or more non-transitory storage media store instructions which, when executed by one or more computing devices, cause performance of an automatic cache management method when a determination is made to store a first set of data in a cache. The method involves determining whether an amount of available space in the cache is less than a predetermined threshold. When the amount of available space in the cache is less than the predetermined threshold, a determination is made as to whether a second set of data has a lower ranking than the first set of data by at least a predetermined amount. When the second set of data has a lower ranking than the first set of data by at least the predetermined amount, the second set of data is evicted. Thereafter, the first set of data is cached.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: A technique performs stream-based storage of data. The technique involves receiving, by processing circuitry of data storage equipment, an incoming flow of data. The technique further involves detecting, by the processing circuitry, different data streams within the incoming flow of data. The technique further involves performing, by the processing circuitry, data placement operations based on the different data streams detected within the incoming flow of data. The data placement operations are configured and operative to place data of each data stream of the different data streams in a different segment of storage provided by a data storage array of the data storage equipment. With data of each data stream being placed in a different segment, the resulting operation is more efficient, e.g., optimized sequential reads and writes, more effective data prefetching, more effective auto-tiering of data, and so on.

Abstract: An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.

Abstract: In one embodiment, a microprocessor, comprising: a translation lookaside buffer (TLB) configured to indicate that a virtual page address corresponding to a physical page address of a page of memory that a memory access instruction is attempting to access is missing in the TLB; a first micro-op corresponding to a first memory access instruction and configured to initiate a first speculative tablewalk based on a miss in the TLB of a first virtual page address; and a second micro-op corresponding to a second memory access instruction, the second micro-op configured to take over an active first speculative tablewalk of the first micro-op at its current stage of processing based on being older than the first micro-op and further based on having a virtual page address and properties that match the first virtual page address and properties for the first memory access instruction.

Abstract: Disclosed herein are techniques for tracking usage of a storage-class memory. In one embodiment, a method includes receiving a first statistics update entry and a second statistics update entry by a memory controller for a memory, and assembling the statistics update entries into a statistics log entry. The first statistics update entry indicates a number of operations performed on a first memory block in the memory, and the second statistics update entry indicates a number of operations performed on a second memory block in the memory. The method also includes determining a persistent memory region in a persistent memory for storing the statistics log entry, and writing the statistics log entry into the persistent memory region, where the statistics log entry persists in the persistent memory region until the statistics log entry is read back through the memory controller.

Abstract: Technologies for directly performing read and write operations on matrix data in a data storage device are disclosed. The data storage device receives a request to perform a read or write operation on matrix data stored in one or more memory units of the data storage device. Each memory unit is associated with a column address for the matrix data. The data storage device determines whether the request specifies to read or write a column or a row in the matrix data. The data storage device performs, in response to a determination that the request specifies to read or write a column in the matrix data, the read or write operation on the matrix data on the column.

Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.