Abstract: An apparatus and method are provided for controlling allocation of information into a cache storage. The apparatus has processing circuitry for executing instructions, and for allowing speculative execution of one or more of those instructions. A cache storage is also provided having a plurality of entries to store information for reference by the processing circuitry, and cache control circuitry is used to control the cache storage, the cache control circuitry comprising a speculative allocation tracker having a plurality of tracking entries. The cache control circuitry is responsive to a speculative request associated with the speculative execution, requiring identified information to be allocated into a given entry of the cache storage, to allocate a tracking entry in the speculative allocation tracker for the speculative request before allowing the identified information to be allocated into the given entry of the cache storage.

Abstract: A method used by a flash memory initialization device for writing boot up information into a memory device including a controller and a flash memory includes: generating the boot up information; generating N block indices by calling a random function based on a first seed; generating M page indices for each of the N block indices; combining the M page indices with each of the N block indices to generate M×N candidate row addresses; and writing the boot up information from the flash memory initialization device into the flash memory by controlling the controller to write the boot up information into M pages belonging to at least one block sequentially based on the M×N candidate row addresses.

Abstract: An apparatus includes a first address converter coupled to a first device and a second device and configured to convert a first n-bit address received from the first device into an m-bit upper address portion and an (n?m)-bit lower address portion and forward the m-bit upper address through a side path and the (n?m)-bit lower address portion through a main path to the second device, m and n are positive integers, and a second address converter configured to assemble the m-bit upper address portion and the (n?m)-bit lower address portion to a second n-bit address that is a representation of the first n-bit address and provide the second n-bit address to a third device.

Abstract: A system include a main computing system, a first peripheral component, and a second peripheral component. The first peripheral component receives analog signals from a hardware elements in a first peripheral system and converts them digital signal values in a local memory. A local processor of the first peripheral component writes the signal values directly into a first memory space in the physical memory of main computing system using direct memory access. The main computing system uses the signal values to generate output signal values that it writes into a second memory space of the physical memory. A second peripheral component directly accesses the second memory space to read the output signal values, and writes the output signal values into a local memory. The second peripheral component generates output analog signals based on the output signal values and provides the analog signals to hardware elements of a second peripheral system.

Abstract: Systems, apparatuses and methods may provide for technology that detects a runtime call to a communication library, wherein the runtime call identifies a memory buffer, determines that a class of service (CLOS) attribute is associated with the memory buffer, and issues a driver instruction to modify the CLOS attribute in response to the runtime call.

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

Abstract: A memory system includes: a memory device including a plurality of memory blocks for storing data; a controller memory including a read data area for storing first data, which is read from a victim memory block among the plurality of memory blocks, and a write data area for storing second data, which is to be written into a target memory block among the plurality of memory blocks; and a controller suitable for reading the first data from the read data area, storing the first data into a host memory, and, when the first data stored in the host memory satisfies a predetermined condition, reading the first data from the host memory and storing the first data into the write data area.

Abstract: Methods and systems for training a neural network include determining a graph representation of a set of neural network training operations based on definition-use chains. A memory allocation queue is determined based on a slack value for each neural network training operation in the graph representation. Memory for each neural network training operation in the memory allocation queue is allocated. Execution of neural network training operations with non-zero slack is delayed to minimize an amount of memory allocated at any one time. Neural network training is executed using the allocated memory for each neural network training operation.

Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.

Abstract: Optimizing containerized applications includes receiving managed runtime code, creating a first container within a managed runtime environment, and executing the managed runtime code in the first container within the managed runtime environment. Responsive to a determination that the managed runtime environment has performed at least one optimization of the managed runtime code to create optimized managed runtime code during a first lifetime of the managed runtime environment, the first container is checkpointed into a first memory image to create a first checkpointed container including the optimized managed runtime code. The first checkpointed container is stored.

Abstract: An apparatus comprises a host device configured to communicate over a network with a storage system. The host device comprises a plurality of communication adapters, each of which comprises a corresponding plurality of input-output (IO) submission queues, and a multi-path input-output (MPIO) driver configured to obtain an IO operation that targets a given logical volume of the storage system and to identify a plurality of paths between the host device and the given logical volume. Each identified path comprises a communication adapter and a corresponding IO submission queue of that communication adapter. An IO load weight and a queue depth weight are determined for each identified path. An adaptive weight for each identified path is determined as a function of the determined IO load weight and the determined queue depth weight for that identified path and a target path is selected from the identified paths based at least in part on the determined adaptive weights.

Abstract: Provided are techniques for providing a global unique identifier for a storage volume. Under control of a storage initiator, a Global Universally Unique Identifier (GUUID) is identified for a storage volume of a storage device in a cloud system storing a plurality of storage devices, wherein the GUUID is generated for use with an ATA over Ethernet (AoE) protocol. The GUUID is stored in bytes of a packet header structure. Metadata is stored in remaining portions of the packet header structure. A request with the packet header structure is sent to a storage target.

Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.

Abstract: The disclosed computer-implemented method for data placement in container-based storage systems may include (i) identifying a file stored within a container-based storage system, where the container-based storage system stores the file as data segments within containers, (ii) receiving, in response to a write operation directed to the file, a request to store within the container-based storage system a new data segment generated by the write operation, (iii) describing the file in terms of a plurality of consecutive slabs, (iv) determining that the new data segment falls within a specified slab, and (v) fulfilling the request to store the new data segment within the container-based storage system by storing the new data segment in a designated container that corresponds to the specified slab in response to determining that the new data segment falls within the specified slab. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Methods and systems for backing up and restoring different point in time versions of a virtual machine, an application, a database, or an electronic file using independently managed snapshot chains are described. In some cases, different point in time versions of a virtual machine may be captured and stored using one or more snapshot chains. Each snapshot chain may correspond with a base image (e.g., a full image snapshot) and one or more incremental files (e.g., two forward incremental files) that derive from the base image. A snapshot chain may be split into a plurality of shards or sub-chains such that the width of each shard or the maximum data size of the files in each shard is less than a threshold data size (e.g., is less than 1 TB). Data operations (e.g., consolidation and reverse operations) may be performed on the individual shards or sub-chains in parallel.

Abstract: With respect to each of one or more entities, a computer sets a sum of an upper-limit NW send quantity and an upper-limit write quantity to a level equal to or lower than an allocation send quantity that is a send quantity allocated for the entity concerned. With respect to each of the one or more entities, the upper-limit NW send quantity is an upper-limit value of the NW send quantity that is the quantity of data to be sent per unit time via an NW I/F of the computer. With respect to each of the one or more entities, an upper-limit write quantity is an upper-limit value of a write quantity that is the quantity of data to be written per unit time to a logical volume recognized by the entity concerned.

Abstract: Techniques expand storage space. Such techniques can create a storage stripe group during a shuffling operation after a storage device being added, without waiting for full completion of the shuffling operation. Such techniques can effectively reduce the waiting time for creating the storage stripe group. Besides, such techniques can support partial mapping of the storage stripe group, such that the storage resources mapped to the storage stripe group can be rapidly utilized.

Abstract: In a data storage system, the available space of a magnetic storage device is divided into multiple sequential write regions for storing sequentially written data, where the regions are each separated from adjacent sequential write regions by a guard space. Object data, such as key-value pairs, are written sequentially to a particular sequential write region, in blocks of data that correspond to the contents of a nonvolatile buffer being flushed to the magnetic storage device. When a key-value pair stored in the magnetic storage device is subsequently updated, the original key-value pair is not overwritten. Instead, the new version of the key-value pair is included in the next block of data to be written to the magnetic storage device, and a mapping table tracks the location of the newest version of each key-value pair stored in the magnetic storage device.

Abstract: A processor of a storage controller stores a parameter according to a command that has been transferred from a front-end unit to a first area in a first memory area and issues notification to the front-end unit regarding an address of a second area in a second memory area which is mapped to the first area, the front-end unit generates a data packet whose destination is the notified address and stores the generated data packet at the address of the second memory area, and an interface unit reads the parameter stored in the first area in the first memory area which is mapped to the second area of the address based on the destination address stored in a header of the data packet which has been stored in the second memory area and executes processing of the system function according to the command.

Abstract: A cache is maintained with write order numbers that indicate orders of writes into the cache, so that periodic partial flushes of the cache can be executed while maintaining write order consistency. A method of storing data into the cache includes receiving a request to write data into the cache, identifying lines in the cache for storing the data, writing the data into the lines of the cache, storing a write order number, and associating the write order number with the lines of the cache. A method of flushing a cache having cache lines associated with write order numbers includes the steps of identifying lines in the cache that are associated with either a selected write order number or a write order number that is less than the selected write order number, and flushing data stored in the identified lines to a persistent storage.