Abstract: According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N?1 SAR cycles, the Nth SAR cycle is performed by setting a Nth tentative analog signal corresponding to a provisional digital code and comparing the Nth tentative analog signal with the sampled analog signal to obtain a Nth comparison result. The (N+1)th SAR cycle is performed by setting a (N+1)th tentative analog signal based on the Nth comparison result, comparing the (N+1)th tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)th comparison result to obtain the output digital code. The Nth and (N+1)th SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.

Abstract: An approach to decoding variable length code (VLC) symbols is described. In one embodiment, a method of decoding VLC symbols is detailed. This method involves obtaining a bitstream sample from a bitstream, and comparing the bitstream sample against a threshold value, to obtain a VLC group number. Information associated with a VLC group is retrieved, using this VLC group number. The current VLC symbol is extracted from the bitstream, using the VLC group information, and the corresponding symbol value is obtained, using the current VLC symbol and the VLC group information.

Abstract: The invention refers to a new keyboard based in a polymeric, copolymeric or composite film (11) with piezo- and pyroelectric properties capable of receiving a tactile signal and giving a respond in the form of an electrical signal. The system described in this invention includes one or more keys (10), being each one of them made by a piezoelectric film (11) with electric conductive contacts, transparent or not, above and below the piezoelectric film and with the inferior layer of grounded electrodes (13).

Abstract: An adjustable analog-digital converter arrangement comprising: an input adapted for receiving an input signal; an analog-digital converter operating by successive approximation, having a signal input coupled with the input, wherein said converter is adapted for converting an analog signal at the signal input into a digital value; an attenuator with an output, wherein an input of said attenuator is coupled to the signal input and is adapted for an amplitude change of signals applied to its input, wherein the amplitude change is controllable by means of a control input, and wherein the attenuator comprises switchable capacitors and forms a part of a first stage of said analog-digital converter; a control circuit having an output coupled to the control input of the attenuator and adapted to initialize, as a function of a comparison of a signal output by the analog-digital converter with a threshold, an automatic adjustment of the attenuation by generating a control signal, and having an output for the output of

Abstract: A digital-analog converter circuit includes: a first digital-analog conversion part that obtains an analog output signal in response to a value of a digital input signal; and a second digital-analog conversion part that generates a control signal in response to a value of a digital gain control input signal externally input, wherein the first digital-analog conversion part adjusts a start voltage or end voltage of the analog output signal based on the digital gain control input signal for controlling the second digital-analog conversion part.

Abstract: Embodiments of the present invention enable compression and decompression of data. Applications of the present invention are its use in embodiments of systems for compression and decompression of GPS long-term Ephemeris (LTE) data, although the present invention is not limited to such applications. In embodiments, the LTE data may be grouped into a set of data values associated with a parameter. In embodiments, a data set may be compressed by using a multi-order differencing scheme. In such a scheme, a set of the differences between values may be compressed because the differences have smaller magnitudes than the values. In embodiments, a multi-order differencing scheme determines how many levels (orders) of differencing may be applied to an original data set before it is compressed. In embodiments, the original data may be recovered from a compressed data set based on the type of multi-order differencing scheme used to generate the compressed data.

Abstract: Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.

Abstract: A system and method are provided for boosting power for a communications link between a base station and a user device, or user equipment, over a communications link channel in a cellular communications network. In one embodiment, the base station determines whether a communications link for a user device located within a sector of a cell served by the base station needs a power boost. If a power boost is needed, the base station provides a power boost for the communications link for the user device and, for each of one or more neighboring sectors that neighbor the sector in which the user device is located, coordinates the power boost in both frequency and time with a power backoff for a downlink to another user device located in a cell center area of the neighboring sector.

Abstract: The present invention relates to a method for using the peak-to-average power ratio (PAR) of signals received by a receiver to control the gain of the receiver for an analogue-to-digital converter (ADC) and/or to control the dynamic range of the ADC.

Abstract: A mechanism for efficient CAVLC coding in a hardware implementation of a H.264 coder is provided. In an embodiment of the present invention, multiple modular CAVLC engines that each process one sub-macroblock of data are used. An assembler engine that combines the CAVLC-encoded sub-macroblock data from each modular CAVLC engine to form a output bit-stream is also provided.

Abstract: A delta-sigma analog-to-digital converter (ADC) circuit improves performance by reducing the amount of noise and other error sampled by the reference switching circuit. The reference is operated such that one or more reference capacitors remain coupled to an input summing node of the ADC input integrator when an input value to a feedback digital-to-analog converter (DAC) indicates that their contribution is not required to apply a reference in the next quantization period. The reference switching network can select from two or more of the following reference options: 1) switch the reference capacitor to apply a charge quanta as per an ordinary switched-capacitor cycle, 2) switch the reference voltage on a second terminal of the reference capacitor to apply an opposite polarity charge quanta, or 3) leave the first terminal of the reference capacitor coupled to the integrator without changing the voltage at the second terminal of the reference capacitor.

Abstract: The present invention is to provide a method for encoding and decoding serial signals formed by a plurality of color lights, which is applied to an encoding/decoding system comprising an encoding device and a decoding device, and comprises steps of generating a driving signal corresponding to at least one first serial code set by the encoding device, so as to drive a multi-color LED to generate a plurality of color lights having different wavelengths and interval time of flash intervals; and receiving the color lights by the decoding device, decoding the color lights according to a decoding procedure of the decoding device for obtaining the first serial code set, and sending an actuation signal when determining that the first serial code set is identical to a second serial code set, so as to provide a variety of more sophisticated, safer and uneasy interfered encoding/decoding functions to various wireless control procedures.

Abstract: A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

Abstract: Methods and systems for parsing and decoding compressed data are provided. Random segments of the compressed data may be decompressed and positioned appropriately in the corresponding uncompressed data set. The methods and systems utilize variable to fixed length (VF) coding techniques. For some applications, the VF coding techniques may be implemented within media encoders, decoders, or combined encoder-decoders (CODECs).

Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A digital-to-analog converter for converting a digital signal into an analog signal is provided. The digital-to-analog converter includes a preprocessing unit, a gain controller, a modulator and an output unit. The preprocessing unit receives and oversamples the digital signal to generate an oversampled signal. The gain controller generates an adjusted signal with a gain function according to a reference signal associated with the oversampled signal when a specific condition is present. The modulator modulates the adjusted signal and generates a modulated signal. The output unit provides the analog signal to a load according to the modulated signal, wherein the analog signal gradually approaches to a specific level according to the gain function when the specific condition is present.

Abstract: There are provided an analog-digital converter circuit capable of performing the same degree of operation as being performed at a high-frequency oscillation pulse using a low-frequency oscillation pulse without using the high-frequency oscillation pulse, a timing signal generating circuit generating a timing signal at the high frequency, and a control device using the circuits. In an analog-digital converter circuit, a periodic signal generating circuit allows the first to j-th pulse counting devices of the N pulse counting devices to count a count value X and allows the other pulse counting devices to count a count value X?1 in each sampling period by sequentially generating N serial periodic signals at a delay time interval of [approximate value of one period (T) of periodic signals]÷N. A digital signal generating circuit converts the analog signal to the digital signal.

Abstract: A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal.

Abstract: A data driver having a positive-polarity reference voltage generation circuit, a positive-polarity decoder, a first amplifier that outputs a positive-polarity gray scale voltage, a negative-polarity reference voltage generation circuit that generates a plurality of negative-polarity reference voltages, a negative-polarity decoder that outputs first to nth negative-polarity reference voltages from among the negative-polarity reference voltages, a negative-polarity amplifier that receives the selected first to nth negative-polarity reference voltages and outputs a negative-polarity gray scale voltage, and an output switch circuit that switches and controls whether to directly connect the first output terminal and the second output terminal to first and second data lines, respectively, or to cross-connect the first output terminal and the second output terminal to the second data line and the first data line, respectively, based on a control signal.