Abstract: A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal.

Abstract: A low-power, high-dynamic range, analog-to-digital (A/D) conversion circuit for converting an analog signal to a digital signal having a controllable amplifier for amplifying the analog signal received at an input of the amplifier in response to a first control signal and for generating an amplified analog signal, a low dynamic range A/D converter for converting the amplified analog signal to an intermediary digital signal, a controllable bit shift register for scaling the intermediary digital signal in response to a second control signal to generate the digital signal, and a gain control component (AGC) for generating the first control signal to cause the amplified analog signal to be within the dynamic range of the A/D converter and for generating the second control signal to cause the scaling to compensate for the amplification by the amplifier.

Abstract: A method, system and computer program product are disclosed for rateless compression of non-binary sources. In one embodiment, the method comprises representing a sequence of non-binary source symbols as a sequence of sets of binary values; selecting a code for compressing the sets of binary values; determining a puncturing pattern, based on the selected code; and puncturing the sets of binary values, in patterns based on the puncturing pattern, to form a sequence of unpunctured values. A sequence of computed syndromes is determined based on the sequence of non-binary source symbols; and the sequence of unpunctured values and the sequence of computed syndromes are combined to form an output stream of data representing said sequence of non-binary source symbols. In one embodiment, none of the sets of binary values is punctured completely, and, for example, each of the sets of binary values may be punctured only partially.

Abstract: The invention is directed at a method and apparatus for determining compression state information which is to be used in the compression of data being transmitted between two communicating parties. The method of determining the compression state information for use in interactively compressing data comprises the steps parsing the data to determine a hierarchical data structure of the data; traversing a shared hierarchical node index to determine common compression state information entries between the hierarchical data structure and the hierarchical node index; and selecting at least one of the common compression state information entries for use in compressing the data.

Abstract: The present invention pertains to calibration in current sensing applications. Power conversion systems such as those used in computer architectures may employ step down converters such as buck converters or other types of converters. The present invention provides calibration processes and devices to account for various parasitic resistances which are found in such systems. A calibration circuit may be coupled to the buck converter or other power conversion to determine a calibrated voltage signal for the output of the power converter. An effective DC resistance may be determined and programmed for use by a control device used. In this way, the parasitic resistances are taken into account to obtain an accurate estimate of the actual current. In turn, this enables power converters and other devices to operate within specification requirements.

Abstract: There is provided an analog-digital conversion cell being an analog-digital conversion cell that performs an N-bit analog-digital conversion (where N is a natural number) and including: a comparison circuit (202) comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2N+1 and equal to or less than 2N+1?1) in accordance with a size of the analog input signal VI; a first logic operation circuit (203) outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×KA+DB0 where a constant KA is a decimal number satisfying a condition of 1<KA<2 and DB0 is a constant, based on the first digital code DA; and an analog operation circuit (201) outputting an analog output signal VO expressed by VO=A×(VI?DA×KA×(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

Abstract: An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.

Abstract: The invention describes a device for the low-distortion conversion, especially amplification, of signals. In one embodiment, the device comprises a digital-to-analog converter having adjustable reference voltages to which an analog-to-digital converter having adjustable reference voltages may be connected upstream. In a further embodiment, the device has a unit, which predistorts a digitized signal, or a digital signal, corresponding to the characteristic transfer line of the amplifier. In a further embodiment, the device has a unit, which equalizes a distorted digitized signal corresponding to the characteristic transfer line of the amplifier stored in the unit. In yet a further embodiment, the device has a digital-to-analog converter operating on the basis of the summation of weighted currents.

Abstract: A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.

Abstract: The digital-to-analog converter in accordance with the present invention comprises an R-2R transistor-only ladder converter and a digital controller. The controller connects to the R-2R transistor-only ladder converter and comprises at least one regulating transistor and at least one shifting transistor. The at least one regulating transistor has an aspect ratio of kR(W/L). The at least one shifting transistor has an aspect ratio of kS(W/L). Setting the aspect ratios kR(W/L) and kS(W/L) of the shifting and regulating transistors adjusts a linear output current waveform to a non-linear waveform. The method to output a non-linear current comprises acts of determining an optimum non-linear output current, dividing a linear output current into multiple sections, determining slopes of the waveform of the output current, adding a controller corresponding to an R-2R transistor-only ladder converter, setting aspect ratios kR(W/L) of regulating transistors and setting an aspect ratios kS(W/L) of shifting transistors.

Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage.

Abstract: A receiver including an automatic gain control module, a digital signal processor module, and a control module. The automatic gain control module has a gain that varies from a nominal value in response to the receiver receiving an input signal. The automatic gain control module is configured to generate a first signal in response to the gain settling at a value different from the nominal value. In response to the input signal not being an interference signal, the digital signal processor module is configured to process the input signal and generate a second signal. Subsequent to the first signal being generated and prior to the second signal being generated, the control module is configured to determine whether the input signal is an interference signal based on whether the second signal is generated within a predetermined time period subsequent to the first signal being generated.

Abstract: A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

Abstract: A lossless coding and/or decoding apparatus and method. The lossless coding apparatus may read a probability model corresponding to each of a plurality of context groups. Here, the probability model stored in a memory may be generated by grouping a context. The lossless coding apparatus may code a symbol using the probability model and generate a bitstream. The lossless coding apparatus may enhance coding efficiency and reduce an amount of space utilized by the memory.

Abstract: A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract: Techniques for encoding data based at least in part upon an awareness of the decoding complexity of the encoded data and the ability of a target decoder to decode the encoded data are disclosed. In some embodiments, a set of data is encoded based at least in part upon a state of a target decoder to which the encoded set of data is to be provided. In some embodiments, a set of data is encoded based at least in part upon the states of multiple decoders to which the encoded set of data is to be provided.

Abstract: An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A power amplifier architecture includes a plurality of non-linear optically driven power amplifier modules. The plurality of non-linear optically driven power amplifier modules are selectively connectable utilizing a programmable algorithm for combining at least two modules of the plurality of non-linear optically driven power amplifier modules in a time sequence yielding a piecewise approximation of a continuous waveform. The power amplifier architecture further includes at least one RF drive selectively connected to at least one of the plurality of non-linear optically driven power amplifier modules via an optical signal link generating a separate drive signal for each of the plurality of non-linear optically driven power amplifier modules.