Abstract: A digital radio system comprises a mixer and an analog-to-digital converter communicative coupled to the mixer. The mixer generates an intermediate frequency signal based at least in part upon a radio frequency signal and a local oscillator signal, wherein the intermediate frequency signal comprises a signal of interest having a particular bandwidth. The analog-to-digital converter generates a digital signal by quantizing the intermediate frequency signal using a sampling frequency that is greater than twice the bandwidth of the signal of interest and less than the frequency of the intermediate frequency signal.

Abstract: Systems and methods for improving output resolution of an optical drive circuit in an optical sensor. The optical sensor circuit includes an optics circuit that generates analog measurement data, a detector circuit that detects the analog measurement data and converts the analog measurement data to a digital measurement data, and a signal processing circuit that demodulates the digital measurement data and generates a segmented digital signal based on the demodulated digital measurement data. The optical sensor circuit further includes an optics drive circuit that generates an analog drive signal based on the segmented digital signal. The analog drive signal is then used to drive the optical circuit.

Abstract: Methods and apparatus, including computer program products, for generating a data stream encoded by means of a Variable Length Coding scheme. Code words for a data stream including a plurality of code words are encoded in accordance with a Variable Length Coding scheme. A separation marker is inserted between encoded data blocks in the data stream.

Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with the value of a signal input to the control terminal. An output signal from the selector in the i-th row and (j?1)th column is input to the first input terminal of the selector in the i-th row and j-th column (1?i?M, 2?j?N+1), a predetermined value of 1 or 0 is input to the second input terminal of the selector in the i-th row and j-th column, and the j-th significant bit of the thermometer code is input to the control terminal of the selector in the i-th row and j-th column.

Abstract: A converter may include an input terminal to receive a first analog signal, a digital-to-analog converter to provide second analog signals related to digital values applied to the digital-to-analog converter, a comparator to receive the first and second analog signals, the comparator comprising a variable gain amplifier to provide an output signal based on a difference between the first and second analog signals, a state machine to receive the output signal of the comparator and generating the digital values applied to the digital-to-analog converter based on the output signal of the comparator, and a controller to selectively set the gain of the variable gain amplifier.

Abstract: Embodiments of the claimed subject matter provide a method and system for performing data compression by encoding input into Exp-Golomb code. In one embodiment, data compression of data input is achieved via encoding as unsigned Exp-Golomb code. The method is achieved by converting the input, determining the position of the most significant bit in the converted input having a non-zero value (MSB), deriving information from the position of the MSB and arithmetically encoding the information to derive a compressed output.

Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

Abstract: An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units.

Abstract: A module (10) connects to a CAN bus in a motor vehicle and converts a CAN message into an analog signal that can be monitored by test equipment. The module also has wireless communication with a PDA (300) via a radio transceiver (28) to allow the PDA to display a converted CAN message and to select different messages for display.

Abstract: A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.

Abstract: A multiple mode digitization system for a non-destructive inspection instrument which makes use of a multiplexing circuit and a single set of analog to digital converters to efficiently digitize analog test signals from a plurality of inputs. In the preferred embodiment, each of the analog to digital converters in the system is driven with an independent and separate clock signal, allowing for propagation delay compensation among the plurality of test signals as well as interleaved sampling such that custom sampling rates can be used for each input without the need for more than one clock frequency. In an alternate embodiment, phase adjustments on the sampling clocks are used only for interleave sampling, and digital filters are used to provide signal propagation delay compensation.

Abstract: Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Abstract: An encoder uses an input file of data and a key to produce an output symbol. An output symbol with key I is generated by determining a weight, W(I), for the output symbol to be generated, selecting W(I) of the input symbols associated with the output symbol according to a function of I, and generating the output symbol's value B(I) from a predetermined value function F(I) of the selected W(I) input symbols. An encoder can be called repeatedly to generate multiple output symbols. The output symbols are generally independent of each other, and an unbounded number (subject to the resolution of I) can be generated, if needed. A decoder receives some or all of the output symbols generated. The number of output symbols needed to decode an input file is equal to, or slightly greater than, the number of input symbols comprising the file, assuming that input symbols and output symbols represent the same number of bits of data.

Abstract: A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.

Abstract: A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: Embodiments of the invention relate to a method and a corresponding circuit for digitizing an analog signal. Applying a nonlinear function to the signal, digitizing the signal and applying the inverse of the nonlinear function to the digital samples improve the digital samples.

Abstract: An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by the analog-to-digital converter. The analog-to-digital converter can use differential or two ramp generators. The analog-to-digital converter can also use ramp generators operated in linear or compressed ramp modes.