Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

Abstract: The present disclosure relates to a solid-state imaging device that can achieve a high S/N ratio at a high sensitivity level without any decrease in resolution, and to an electronic apparatus. In the upper layer, the respective pixels of a photoelectric conversion unit that absorbs light of a first wavelength are tilted at approximately 45 degrees with respect to a square pixel array, and are two-dimensionally arranged in horizontal directions and vertical directions in an oblique array. The respective pixels of a photoelectric conversion unit that is sensitive to light of a second or third wavelength are arranged under the first photoelectric conversion unit. That is, pixels that are ?2 times as large in size (twice as large in area) and are rotated 45 degrees are arranged in an oblique array. The present disclosure can be applied to solid-state imaging devices that are used in imaging apparatuses, for example.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from ?1.0 ?m to 1.0 ?m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.

Abstract: Systems and techniques enable monitoring one or more devices connected to an electrical power distribution system. In some implementations, a probe waveform is injected into a circuit of an electrical power distribution system. An output signal of the injected probe waveform is extracted from the circuit of the electrical power distribution system and, based on the extracted output signal of the injected probe waveform, dispersion values for the branch circuit are determined. The dispersion values indicate a variation of magnitude of an impedance of the branch circuit across different values of phase of the impedance. Based on the dispersion values for the branch circuit, at least one characteristic of a device connected to the branch circuit is determined. An association between the at least one characteristic of the device connected to the branch circuit and the corresponding dispersion values is stored in at least one computer memory.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

Abstract: An organic light-emitting display device includes: first and second pixel electrodes (PEs); a pixel-defining layer (PDL) disposed on the first and second PEs, the pixel-defining layer including first and second openings respectively exposing the first and second PEs; first and second intermediate layers (ILs) respectively disposed on the first and second PEs exposed via the first and second openings, each of the first and second ILs including an emission layer; first and second opposite electrodes (OEs) respectively disposed on the first and second ILs, the first and second OEs having an island-shaped pattern; first and second protective layers (PLs) respectively disposed on the first and second OEs, the first and second PLs having an island-shaped pattern; and a connection layer disposed on the first and second PLs, the connection layer electrically connecting the first and second OEs to one another.

Abstract: A display device is disclosed, which includes: a substrate; a first metal conductive layer disposed on the substrate; a semiconductor layer disposed on the first metal conductive layer; and a second metal conductive layer disposed on the semiconductor layer and including a data line, a first part and a second part separated from the first part, the data line with a data extending direction connected to the second part. A first extending direction is a direction that the first part extends toward the second part, a first region is a region that the first part overlaps the first metal conductive layer, the first part has a first maximum breadth outside the first region along the data extending direction and a second maximum breadth inside the first region along a direction substantially perpendicular to the first extending direction, and the first maximum breadth is greater than the second maximum breadth.

Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.

Abstract: According to one embodiment, an organic semiconductor device includes a supporting substrate, a plurality of organic EL light emitting elements, a first barrier layer, a flattening layer, and a second barrier layer. The flattening layer exists sporadically and makes gentle in inclination steep elevation change present in the surface of the first barrier layer. The first barrier layer and the second barrier layer are made of moisture penetration preventive material.

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Abstract: The present disclosure provides an OLED display apparatus and a method for producing the same, and a color filter substrate and a method for producing the same. The OLED display apparatus comprises: a TFT array substrate; a luminescent structure layer provided on the TFT array substrate, wherein light emitted from the luminescent structure layer is infrared light; and a light conversion layer located on the luminescent structure layer. The light conversion layer comprises a plurality of pixel areas, each of which is at least provided with three light conversion units, which are a red light conversion unit formed of an upconversion luminescent material emitting red light after stimulation by infrared light, a green light conversion unit formed of an upconversion luminescent material emitting green light after stimulation by infrared light, and a blue light conversion unit formed of an upconversion luminescent material emitting blue light after stimulation by infrared light.

Abstract: A method for manufacturing a semiconductor device includes forming a first plurality of fins in a first device region on a substrate, forming a second plurality of fins in a second device region on the substrate, forming bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of fins in the first and second device regions, forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants, and forming a plurality of doped regions in the first and second plurality of fins in the first and second device regions, wherein the plurality of doped regions in the first device region extend to a greater height on the first plurality of fins than the plurality of doped regions in the second device region on the second plurality of fins.

Abstract: A flexible, thin film electronic device comprising a module cut from a web provided with one or more cells along substantially the whole of its length wherein the cells comprise a first electrode layer, a second electrode layer and one or more active layers provided between the electrode layers characterised in that the module includes one or more edge portions wherein an edge of the first electrode layer and an edge of the second electrode layer are each substantially coincident with an edge of the web.

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer.

Abstract: A method of fabricating a gate all around semiconductor device is provided.

Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.