Patents Examined by Peter Bradford
  • Solid-state imaging device, manufacturing method of solid-state imaging device and electronic apparatus
    Patent number: 11315976
    Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 26, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Takahiro Kawamura
  • Organic light emitting diode display and a system of a mask unit and a substrate for making the same
    Patent number: 11309356
    Abstract: An organic light emitting diode display includes a first electrode, a pixel defining layer positioned on the first electrode and including a first opening having a first polygonal shape opening the first electrode, and a first organic emission layer positioned on the pixel defining layer through the first electrode corresponding to the first opening and including a first chamfer adjacent to a corner of the first opening.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 19, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Oh-Seob Kwon
  • Device with heteroepitaxial structure made using a growth mask
    Patent number: 11296206
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 5, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same
    Patent number: 11296277
    Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Ahn, Oik Kwon, Jeonghee Park, Kihyun Hwang
  • Display panel and display device
    Patent number: 11296161
    Abstract: Disclosed are a display panel and a display device. The display panel includes a display area and an opening area, where the opening area is configured to accommodate an optical component, and the display area at least partially surrounds the opening area; where the display area includes edge pixel defining structures and conventional pixel defining structures, and the edge pixel defining structures are closer to the opening area than the conventional pixel defining structures; where a reflectivity of each edge pixel defining structure is greater than a reflectivity of each conventional pixel defining structure.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: April 5, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Youwei Wang, Song Zhang, Peng Cai
  • Method of making heteroepitaxial structures and device formed by the method
    Patent number: 11296208
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 5, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Method of forming a seed area and growing a heteroepitaxial layer on the seed area
    Patent number: 11296207
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 5, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Heat releasing semiconductor chip package and method for manufacturing the same
    Patent number: 11289345
    Abstract: A method for manufacturing a heat releasing semiconductor chip package includes attaching a first surface of a semiconductor chip onto an insulating film, injecting a coating liquid onto a second surface of the semiconductor chip to form a liquefied coating layer and curing the liquefied coating layer to form a heat releasing layer. The coating liquid includes a liquefied molding compound for heat releasing and fine alumina particles. Therefore, the heat releasing semiconductor chip package and method for manufacturing the semiconductor chip package form a heat releasing layer in direct contact with the semiconductor chip to maximize a heat releasing effect.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 29, 2022
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jo Han Kim, Hee Jin Park, Kyeong Su Kim, Jae Jin Lee
  • Flexible display with groove in bending area
    Patent number: 11289680
    Abstract: A flexible display and manufacturing method thereof are disclosed. In one aspect, the flexible display includes a flexible substrate including a bending area, an insulating layer disposed on the flexible substrate, and at least one groove in the insulating layer within the bending area. The flexible display also includes a stress relaxation layer disposed on the at least one groove and a plurality of wires formed over the insulating layer and the stress relaxation layer.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nam Jin Kim
  • Spin-orbit-torque magnetoresistive memory cell with integrated selector elements and method of making the same
    Patent number: 11271035
    Abstract: A spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device includes a SOT MRAM cell containing a first two terminal selector element, a nonmagnetic metallic assist plate, and a magnetic tunnel junction located between the first two terminal selector element and the nonmagnetic metallic assist plate, and a circuit selection element selected from a transistor or a second two terminal selector element electrically connected to the nonmagnetic metallic assist plate of the SOT MRAM cell.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 8, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lei Wan, Jordan Katine, Neil Robertson
  • Pixel arrangement structure with misaligned repeating units, display substrate, display apparatus and method of fabrication thereof
    Patent number: 11264430
    Abstract: A pixel arrangement structure are provided, which includes a plurality of repeating units. Each of the plurality of repeating units includes two first sub-pixels, one second sub-pixel, and one third sub-pixel. Each of the first sub-pixel, the second sub-pixel and the third sub-pixel includes a pixel defining layer, the pixel defining layer includes a pixel defining layer opening to define an effective light emitting region of each sub-pixel; a plurality of first sub-pixels are arranged along the second direction to form a plurality of first sub-pixel groups, orthographic projections of pixel defining layer openings of the first sub-pixels in adjacent ones of the plurality of first sub-pixel groups on a straight line parallel to the second direction do not overlap each other.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 1, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lujiang Huangfu, Libin Liu, Fengli Ji, Xiaodan Jin, Yinan Liang, Mei Li, Jie Zhang, Chang Luo, Jianpeng Wu, Hongli Wang
  • Gallium nitride electromagnetic pulse arrestor
    Patent number: 11227844
    Abstract: A GaN diode EMP arrestor exhibits breakdown in <10 ns at reverse-bias voltage >20 kV. Additionally, the arrestor exhibits avalanche ruggedness at 1 kA/cm2 in a 1 mm2 device (i.e. 10 A absolute current) over a period of 500 ns following the onset of breakdown. Finally, the specific on-resistance in the forward direction is <20 m? cm2.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 18, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert Kaplar, Jack David Flicker, Olga Lavrova
  • Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
    Patent number: 11211384
    Abstract: A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Hybrid package
    Patent number: 11189557
    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: November 30, 2021
    Assignee: NXP USA, INC.
    Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
  • Transistor having reduced contact resistance
    Patent number: 11189693
    Abstract: An integrated semiconductor device having a substrate, a bottom source or drain (S/D) structure formed on the substrate. In addition, the device includes a fin extending from the bottom S/D structure and a gate formed around the fin. A top S/D structure is formed on top of the fin. The top S/D structure includes a recessed top S/D surface and a silicide layer covering a top portion of the recess. A contact is communicatively coupled to a surface of the silicide layer of the recessed top S/D surface of the top S/D structure.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Magnetoresistive stack/structure including metal insertion substance
    Patent number: 11189781
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 30, 2021
    Assignee: Everspin Technologies, Inc.
    Inventor: Sumio Ikegawa
  • Dynamic precursor dosing for atomic layer deposition
    Patent number: 11180850
    Abstract: Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 23, 2021
    Assignee: Lam Research Corporation
    Inventors: Purushottam Kumar, Adrien LaVoie, Jun Qian, Hu Kang, Ishtak Karim, Fung Suong Ou
  • Gate electrode layout with expanded portions over active and isolation regions
    Patent number: 11183576
    Abstract: Apparatuses with a gate electrode in a semiconductor device are described. An example apparatus includes an active region surrounded by an isolation region, and a gate electrode extending in a first direction to pass over the active region. The gate electrode includes a body gate portion over the active region, the body gate portion having a first gate length in a second direction perpendicular to the first direction, a lead-out portion over the isolation region, the lead-out portion having a second gate length in the second direction, the second gate length being greater than the first gate length, and a hammer-head portion having a first end in contact with the body gate portion and a second end opposite to the first end in contact with the hammer-head portion.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Matsumoto, Ryota Suzuki, Makoto Sato
  • Deposition of metal films with tungsten liner
    Patent number: 11171045
    Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 9, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Yu Lei, Sang-Hyeob Lee, Chris Pabelico, Yi Xu, Tae Hong Ha, Xianmin Tang, Jin Hee Park
  • Memory device with low density thermal barrier
    Patent number: 11158561
    Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: October 26, 2021
    Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs