Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.

Abstract: An electronic device, including a substrate, a thin film transistor, a first insulating layer, a pixel electrode, and a common electrode, is provided. The thin film transistor is disposed on the substrate and includes an electrode. The first insulating layer is disposed on the thin film transistor and includes a first opening. The pixel electrode is disposed on the first insulating layer and electrically connected to the electrode through the first opening. The common electrode is disposed on the pixel electrode and in the first opening.

Abstract: A method for manufacturing an image display device includes: providing a second substrate that comprises a first substrate, and a semiconductor layer on the first substrate, the semiconductor layer comprising a light-emitting layer; providing a third substrate comprising a circuit, the circuit comprising a circuit element; bonding the semiconductor layer to the third substrate; forming a light-emitting element by etching the semiconductor layer; covering the light-emitting element with a light-transmissive insulating member; and forming a wiring layer electrically connecting the light-emitting element to the circuit element; wherein: the light-emitting element has a light-emitting surface opposite to a surface of the light-emitting element that is bonded to the third substrate; and the insulating member is configured to cause light radiated from the light-emitting element to have a light distribution in a normal direction of the light-emitting surface toward a light-emitting surface side.

Abstract: A display substrate and a display panel are provided. The display substrate includes: a base including a front surface, a back surface and a side surface; a driving circuit layer disposed on the front surface; a back electrode disposed on the back surface; a side printed wire electrically connected to the driving circuit layer, the side printed wire extends to the back electrode from the side surface and is electrically connected to the back electrode, the side printed wire includes a wire top portion located on a side of the driving circuit layer facing away from the base; and a bonding adhesive layer disposed overlying the side of the driving circuit layer facing away from the base, the bonding adhesive layer is further in contact with and covers the wire top portion. The display substrate and the display panel can solve a problem of excessive height in a non-display area.

Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides a Single-Photon Avalanche Detector (SPAD) circuit that includes a junction region that is characterized by a wave-shaped profile that corresponds to a plurality of filling structures. The wave-shaped profile is associated with electric field and breakdown voltage uniformity. There are other embodiments as well.

Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.

Abstract: A display device includes a first substrate including a display area and a non-display area adjacent to the display area, a first voltage line disposed on the first substrate and supplying a first voltage, a second substrate disposed on the first voltage line, and a thin film transistor layer disposed on the second substrate and comprising a plurality of thin film transistors and a second voltage line disposed in the non-display area and electrically connected to the first voltage line through a first contact hole penetrating the second substrate.

Abstract: Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate, with word lines arranged at intervals in the substrate, and trenches between adjacent word lines; a bit line contact layer, wherein the bottom surface of the bit line contact layer is in contact with the bottom surface of the trench, and the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the trench; the conductive layer is in contact with the non-planar contact portion of the bit line contact layer. The embodiments of the present application are beneficial in reducing the resistance of the bit line itself including the bit line contact layer and the conductive layer, thereby helping to improve the electrical performance of the semiconductor structure.

Abstract: The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of field effect transistors, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.

Abstract: A finger-type semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral power supply strips. The second conductive structure includes longitudinal second conductive strips and P lateral power supply strip(s). The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit (IC) layer; and the longitudinal first conductive strips include a first row of strips and a second row of strips. The lateral power supply strips are located in a second IC layer, and coupled to the first and second rows of strips through vias. The P lateral power supply strip(s) is/are located in the second IC layer, and include(s) a first-capacitor-group power supply strip that is coupled to K strip(s) of the longitudinal second conductive strips through K via(s). The P and K are positive integers.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed outside of the display area. The display area includes a plurality of pixels. The display device further includes an inorganic insulating layer disposed in the display area. The inorganic insulating layer includes a groove disposed in a region between the plurality of pixels. The display device further includes an organic material layer filling the groove, a first connection wiring, and a second connection wiring. The first connection wiring is disposed on the organic material layer, overlaps the plurality of pixels, and extends in a second direction. The second connection wiring is insulated from the first connection wiring, and extends in a first direction that crosses the second direction.

Abstract: A display device includes a display member and a touch member disposed on the display member. The touch member includes a first touch insulating disposed on the display member, a first touch conductive layer disposed on the first touch insulating layer and including a touch bridge electrode, a second touch insulating layer disposed on the first touch conductive layer, including an organic material, and including a first contact hole penetrating the second touch insulating layer in a thickness direction, a second touch conductive layer disposed on the second touch insulating layer and including a first lower sensing line overlapping the second touch bridge electrode, and a third touch conductive layer disposed on the second touch conductive layer and including a first upper sensing line overlapping the first lower sensing line. A width of the first upper sensing line is greater than a width of the first lower sensing line.

Abstract: An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes a substrate and a thin film transistor layer arranged on the substrate. The thin film transistor layer includes a plurality of thin film transistors. The thin film transistors each include an active layer, a source/drain, a first gate, a second gate, and a first insulating layer. The first gate and the second gate are electrically connected through the through hole. The problems of difficulty in etching and excessively long etching time are avoided while reducing the gate resistance of the thin film transistor.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The present invention uses an inkjet printing method to construct a two-dimensional nanomaterial as a photosensitive film, and adjusts a composition of the nanomaterial to construct a photoelectric film with high gain, which is then combined with a high mobility film to construct a display device with high mobility and broad spectrum light response.

Abstract: The present application relates to an array substrate and a preparation method thereof, and a display device; wherein the array substrate comprises a substrate and a plurality of sub-pixels distributed in an array on the substrate, the sub-pixels comprising M oxide thin film transistors, each oxide thin film transistor comprising a modulation electrode, a gate electrode, a source electrode and a drain electrode arranged in a stack, wherein the modulation electrodes of the M oxide thin film transistors are electrically connected to each other as a modulation layer, and the modulation layer is electrically connected to the gate electrode through N first vias, wherein M and N are both integers, and N<M.

Abstract: The present disclosure provides a display device and an electronic device. The display device includes a display panel and a source driving chip. The display panel includes a plurality of traces in a fan-shaped distribution. A plurality of signal output terminals and a plurality of compensation traces are disposed in the source driving chip. The compensation traces are configured to reduce a resistance difference among the plurality of traces in a fan-shaped distribution, and each signal output terminal is electrically connected to a corresponding one of the traces in a fan-shaped distribution using one corresponding compensation trace.

Abstract: To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. A semiconductor device includes an oxide semiconductor film, a gate electrode, an insulating film over the gate electrode, the oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film, include the same element. The first oxide semiconductor film includes a region having lower crystallinity than the second oxide semiconductor film.

Abstract: A transparent display substrate, a transparent display panel and a display device. The display substrate includes at least one pixel unit. The at least one pixel unit includes at least three sub-pixel groups emitting light of different colors. The sub-pixel groups includes at least two sub-pixels, and the sub-pixels include a first electrode, a light-emitting structure block located on the first electrode, and a second electrode located on the light-emitting structure block. In the at least one pixel unit, two first electrodes of two adjacent sub-pixels in a sub-pixel group are electrically connected by a first connecting portion, two first electrodes of two sub-pixels in another of the sub-pixel groups are electrically connected by a second connecting portion. The second connecting portion at least partially surrounds sides of the sub-pixels in other sub-pixel groups. The first connecting portion and the second connecting portion are located in a same layer.

Abstract: A magnetoresistance effect element includes a magnetic recording layer which includes a ferromagnetic material, a non-magnetic layer laminated on the magnetic recording layer, and a magnetization reference layer which is laminated on the non-magnetic layer. The magnetic recording layer includes a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in order from the non-magnetic layer. The first ferromagnetic layer and the second ferromagnetic layer are antiferromagnetically coupled to each other.