Patents Examined by Peter M Albrecht
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Patent number: 12225798Abstract: A transparent display substrate, a transparent display panel and a display device. The display substrate includes at least one pixel unit. The at least one pixel unit includes at least three sub-pixel groups emitting light of different colors. The sub-pixel groups includes at least two sub-pixels, and the sub-pixels include a first electrode, a light-emitting structure block located on the first electrode, and a second electrode located on the light-emitting structure block. In the at least one pixel unit, two first electrodes of two adjacent sub-pixels in a sub-pixel group are electrically connected by a first connecting portion, two first electrodes of two sub-pixels in another of the sub-pixel groups are electrically connected by a second connecting portion. The second connecting portion at least partially surrounds sides of the sub-pixels in other sub-pixel groups. The first connecting portion and the second connecting portion are located in a same layer.Type: GrantFiled: October 6, 2021Date of Patent: February 11, 2025Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.Inventors: Chuanzhi Xu, Lu Zhang
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Patent number: 12225830Abstract: A magnetoresistance effect element includes a magnetic recording layer which includes a ferromagnetic material, a non-magnetic layer laminated on the magnetic recording layer, and a magnetization reference layer which is laminated on the non-magnetic layer. The magnetic recording layer includes a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in order from the non-magnetic layer. The first ferromagnetic layer and the second ferromagnetic layer are antiferromagnetically coupled to each other.Type: GrantFiled: December 6, 2021Date of Patent: February 11, 2025Assignee: TDK CORPORATIONInventors: Shogo Yamada, Minoru Ota, Tatsuo Shibata
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Patent number: 12218148Abstract: Provided is a display module including a glass substrate, a thin film transistor (TFT) layer provided on a front surface of the glass substrate, a driving circuit provided on a rear surface of the glass substrate and configured to drive the TFT layer, a plurality of light emitting diodes (LED) electrically connected to the TFT layer, a plurality of first connection pads provided at intervals in a portion of the front surface of the glass substrate and electrically connected to a TFT circuit provided in in the TFT layer, a plurality of second connection pads provided at intervals in a portion of the rear surface of the glass substrate and electrically connected to the driving circuit, and a plurality of side wirings extending from the lateral surface of the glass substrate to a portion of an insulating layer and extending to another portion of the insulating layer.Type: GrantFiled: October 27, 2021Date of Patent: February 4, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongyun Kim, Hosuk Kang, Jinwoo Jung, Changjoon Lee, Tackmo Lee, Gyun Heo, Soonmin Hong
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Patent number: 12211943Abstract: A display device includes a substrate, a semiconductor layer, an insulating layer, and a conductive layer. The semiconductor layer is disposed on the substrate, includes a channel of a first transistor, and includes a channel of a second transistor. The insulating layer is disposed on the semiconductor layer. The conductive layer is disposed on the insulating layer, includes a gate electrode of the first transistor, and includes a gate electrode of the second transistor. The channel of the first transistor includes a first first-element impurity ion and a second-element impurity ion different from the first first-element impurity ion. The channel of the second transistor includes a second first-element impurity ion identical to the first first-element impurity ion.Type: GrantFiled: February 4, 2022Date of Patent: January 28, 2025Assignee: Samsung Display Co., Ltd.Inventors: Jong Oh Seo, Jang Hyun Kim, Jae Woo Jeong, Jong Hoon Choi
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Patent number: 12207508Abstract: Provided in the present disclosure are a display panel and a display device. The display panel comprises: a base substrate; multiple contact electrodes, arranged on the base substrate in a non-display region of the display panel; an inorganic film layer, arranged on the side of the contact electrodes in proximity to the base substrate; the inorganic film layer comprising an inorganic material; an organic film layer, arranged on the side of the contact electrodes away from the base substrate; and a barrier layer, arranged on the side of the organic film layer away from the base substrate; the barrier layer comprising an inorganic material; and, the organic film layer being provided with openings in at least some gaps between adjacent contact electrodes.Type: GrantFiled: March 9, 2021Date of Patent: January 21, 2025Assignees: Chongqing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Tianlong Zhao, Hyoungseok Park, Zifeng Wang, Dawei Shi
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Patent number: 12199217Abstract: A light-emitting chip includes a light-emitting unit, first and second electrode units. The light-emitting unit includes first and second conductivity type semiconductor layers and an active layer. The first electrode unit includes two first electrodes which are spaced apart from each other by a first distance, and which are electrically connected to the first conductivity type semiconductor layer. The second electrode unit includes two second electrodes electrically connected to the second conductivity type semiconductor layer. The first and second electrode units are spaced apart from each other by a second distance, and the first distance is greater than the second distance.Type: GrantFiled: January 4, 2022Date of Patent: January 14, 2025Assignee: LUMINUS (XIAMEN) CO., LTD.Inventors: Xiaoqiang Zeng, Kunte Lin, Jianfeng Yang, Kaiqing Xu, Shao-Hua Huang
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Patent number: 12191293Abstract: A display device and a method for fabricating the same are provided. The display device includes a support substrate, a light-emitting chip, and a thin film transistor. The light-emitting chip is disposed on a side of the support substrate. The thin film transistor is disposed on a side of the light-emitting chip away from the support substrate. The thin film transistor is connected to the light-emitting chip.Type: GrantFiled: December 16, 2021Date of Patent: January 7, 2025Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Shijuan Yi
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Patent number: 12191431Abstract: A display device includes a light emitting element and an optical adjustment layer over the light emitting element. The optical adjustment layer includes a reflective film, a light transmitting wall over the reflection film, and a light transmitting film in contact with a side surface of the reflective film and a side surface of the light transmitting wall. A refractive index of the light transmitting wall is larger than a refractive index of the light transmitting film.Type: GrantFiled: January 28, 2022Date of Patent: January 7, 2025Assignee: Japan Display Inc.Inventor: Osamu Itou
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Patent number: 12183745Abstract: A display panel and a display apparatus includes sub-pixels, and First and second regions arranged along a first direction. First sub-pixel groups in the first region and second sub-pixel groups in the second region are arranged along the first direction, and each include at least two sub-pixels arranged along the second direction. A number of the sub-pixels in the second sub-pixel group close to the first region is greater than a number of the sub-pixels in the second sub-pixel groups away from the first region. The first sub-region of the second region is closer to the first region than the second sub-region. From the first region to the second region, a variation rate of the numbers of the sub-pixels in the second sub-pixel groups in the first sub-region is greater than a variation rate of the numbers of the sub-pixels in the second sub-pixel groups in the second sub-region.Type: GrantFiled: December 28, 2021Date of Patent: December 31, 2024Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.Inventors: Kunfeng Zhang, Yiqiang Lin, Wei Wu, Boping Shen
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Patent number: 12178147Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.Type: GrantFiled: October 16, 2022Date of Patent: December 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hai-Dang Trinh, Fa-Shen Jiang, Hsing-Lien Lin, Chii-Ming Wu
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Patent number: 12176410Abstract: A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.Type: GrantFiled: August 31, 2021Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chung-Liang Cheng
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Patent number: 12178039Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.Type: GrantFiled: December 7, 2021Date of Patent: December 24, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Hsih-Yang Chiu
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Patent number: 12170336Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.Type: GrantFiled: December 2, 2021Date of Patent: December 17, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanghee Lee, Sangwook Kim
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Patent number: 12154979Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.Type: GrantFiled: October 7, 2021Date of Patent: November 26, 2024Assignee: IMEC VZWInventor: Aryan Afzalian
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Patent number: 12154892Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.Type: GrantFiled: December 6, 2023Date of Patent: November 26, 2024Assignee: AUO CorporationInventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
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Patent number: 12148842Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.Type: GrantFiled: March 10, 2023Date of Patent: November 19, 2024Assignee: JAPAN DISPLAY INC.Inventors: Masataka Ikeda, Hirotaka Hayashi, Hitoshi Tanaka
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Patent number: 12150320Abstract: Provided is a photoelectric conversion element includes two electrodes forming a positive electrode and a negative electrode, at least one charge blocking layer arranged between the two electrodes, and a photoelectric conversion layer arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer or a hole blocking layer, and a potential of the charge blocking layer is bent.Type: GrantFiled: June 13, 2023Date of Patent: November 19, 2024Assignee: SONY GROUP CORPORATIONInventors: Yukio Kaneda, Ryoji Arai, Toshiki Moriwaki
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Patent number: 12148767Abstract: A display device includes a display layer comprising pixels, each of the pixels having at least one thin-film transistor, a connection line electrically connected to the at least one thin-film transistor, the connection line being exposed on a lower surface of the display layer through a first contact hole formed in the display layer, a barrier layer disposed on the lower surface of the display layer and including a second contact hole connected to the first contact hole, a lead line disposed on a lower surface of the barrier layer and electrically connected to the connection line through the second contact hole, a pad part disposed on the lower surface of the barrier layer and electrically connected to the lead line, and a lower film overlapping the lower surface of the barrier layer and the lead line.Type: GrantFiled: August 12, 2021Date of Patent: November 19, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Se Hoon Jeong, Seung Wook Kwon, Jae Sik Kim, Woo Yong Sung, Seo Yeon Lee, Ung Soo Lee, Ja Min Lee, Jeong Seok Lee, Seung Gun Chae, Seung Yeon Chae
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Patent number: 12144185Abstract: A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.Type: GrantFiled: February 2, 2022Date of Patent: November 12, 2024Assignees: Sandisk Technologies, Inc., POHANG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Oleksandr Mosendz, Hyunsang Hwang, Jangseop Lee, Raghuveer S. Makala
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Patent number: 12142613Abstract: An array substrate includes a substrate, a plurality of first signal lines, a plurality of traces, a plurality of second signal lines, and a plurality of switching elements. The first signal lines are disposed on the substrate along a first direction. The traces are disposed on the substrate along a second direction different from the first direction, and one trace is electrically connected to one first signal line and crosses another one first signal line. The second signal lines are disposed on the substrate along the second direction, the second signal lines cross the first signal lines, and the traces and the second signal lines are formed of different conductive layers. The switching elements are disposed on the substrate, and one of the switching elements is electrically connected to a corresponding one first signal line and a corresponding one second signal line.Type: GrantFiled: March 16, 2022Date of Patent: November 12, 2024Assignee: HANNSTOUCH SOLUTION INCORPORATEDInventor: Sheng-Chia Lin