Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.

Abstract: A display device includes a display layer comprising pixels, each of the pixels having at least one thin-film transistor, a connection line electrically connected to the at least one thin-film transistor, the connection line being exposed on a lower surface of the display layer through a first contact hole formed in the display layer, a barrier layer disposed on the lower surface of the display layer and including a second contact hole connected to the first contact hole, a lead line disposed on a lower surface of the barrier layer and electrically connected to the connection line through the second contact hole, a pad part disposed on the lower surface of the barrier layer and electrically connected to the lead line, and a lower film overlapping the lower surface of the barrier layer and the lead line.

Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

Abstract: Provided is a photoelectric conversion element includes two electrodes forming a positive electrode and a negative electrode, at least one charge blocking layer arranged between the two electrodes, and a photoelectric conversion layer arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer or a hole blocking layer, and a potential of the charge blocking layer is bent.

Abstract: There is provided a resonator structure that obtains a highly accurate optical spectrum. The resonator structure includes a stacked structure that includes a semiconductor layer, a first resonator, a first reflection layer, a second resonator, a second reflection layer stacked in this order, allows light of a specific wavelength band to be transmitted therethrough, the semiconductor layer having a first average refractive index, the first resonator having a second average refractive index lower than the first average refractive index, and the first reflection layer having a third average refractive index higher than the second average refractive index.

Abstract: An array substrate includes a substrate, a plurality of first signal lines, a plurality of traces, a plurality of second signal lines, and a plurality of switching elements. The first signal lines are disposed on the substrate along a first direction. The traces are disposed on the substrate along a second direction different from the first direction, and one trace is electrically connected to one first signal line and crosses another one first signal line. The second signal lines are disposed on the substrate along the second direction, the second signal lines cross the first signal lines, and the traces and the second signal lines are formed of different conductive layers. The switching elements are disposed on the substrate, and one of the switching elements is electrically connected to a corresponding one first signal line and a corresponding one second signal line.

Abstract: A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Abstract: A display panel includes: pixels, first wirings arranged in a second direction, second wirings arranged in a first direction, and first and second light-shielding strips that are disposed in a first region. First wirings passing through the first region include first wiring groups, and first wirings in each first wiring group are gathered in the first region to constitute a first gathering portion. Second wirings passing through the first region include second wiring groups, and second wirings in each second wiring group are gathered in the first region to constitute a second gathering portion. An orthographic projection of the first gathering portion on the display surface is located within an orthographic projection of a corresponding first light-shielding strip on the display surface. An orthographic projection of the second gathering portion on the display surface is located within an orthographic projection of a corresponding second light-shielding strip on the display surface.

Abstract: A transistor for detecting gases in the ambient air. The transistor includes a plurality of electrodes with one electrode being a gate electrode. At least one electrode is individually coated by a ceramic. An ionogel connects all electrodes with each other, the ionogel being an ionic liquid immobilized by a matrix. The use of such a transistor as an air-quality sensor is described. A process for making the transistor is also described. The process includes providing a plurality of electrodes, wherein one of the electrodes is a gate electrode; individually depositing a ceramic precursor on at least one of the plurality of electrodes; and connecting the plurality of electrodes with an ionogel, the ionogel being an ionic liquid immobilized by a matrix. A transistor produced by the process is also described.

Abstract: Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Abstract: To provide a semiconductor film capable of realizing further enhancement of photoelectric conversion efficiency. The semiconductor film includes semiconductor nanoparticles and a compound represented by the following general formula (1), in which the compound represented by the general formula (1) is coordinated to the semiconductor nanoparticles. (In the general formula (1), X represents —SH, —COOH, —NH2, —PO(OH)2, or —SO2(OH), A1 represents —S, —COO, —PO(OH)O, or —SO2(O), and n is an integer of 1 to 3. B1 represents Li, Na, or K.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a semiconductor substrate; determining a position of a bit line contact opening on a top surface of the semiconductor substrate and a top surface of a first dielectric layer; etching an active region, the first dielectric layer and an isolation structure exposed by the bit line contact opening according to the position of the bit line contact opening until the active region is etched to a preset depth to form a bit line contact window; and forming a second dielectric layer on a surface of the isolation structure and a surface of the first dielectric layer that have a depth greater than a depth of a surface of the active region in the bit line contact window.

Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.

Abstract: A display panel and a method for fabricating the same are provided. In the display panel, an undercut structure is formed below a second auxiliary electrode, so that a cathode electrode and a first auxiliary electrode have an overlapping region, and the cathode electrode and the first auxiliary electrode are connected.

Abstract: A tiled display device includes a plurality of display devices including a plurality of display areas including pixels, and a coupling area between adjacent display areas from among the plurality of display areas. Each of the plurality of display devices includes: a substrate including a first portion configured to support the display area, a second portion extending from the first portion to be bent, and a third portion extending from the second portion, a display layer on the first portion of the substrate and including the pixels, a connection line at an edge of the first portion of the substrate and connected to the plurality of pixels, a pad portion on the third portion of the substrate, a fan-out line on the second portion of the substrate and connected between the pad portion and the connection line, and pattern holes penetrating the second portion of the substrate.

Abstract: Provided is a display device including a light emitting unit that can emit a plurality of types of light having different wavelengths to the outside at a desired ratio with high intensity without increasing manufacturing costs in proportion to a number of pixels even when the number of pixels increases. Provided is a display device including a light emitting unit in which a plurality of types of PiN junction-type light emitting diodes that emit light having different wavelengths are arranged on the same substrate, and at least one type among the plurality of types of light emitting diodes has an active layer containing a rare earth element. Provided is a display device in which a plurality of types of light emitting diodes are sequentially stacked on the surface of a substrate, and a light emitting layer for one color is formed to overlap at least a portion of a light emitting layer for another color.

Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; a first semiconductor layer on the base substrate; and a second semiconductor layer on a side of the first semiconductor layer away from the base substrate. The display substrate further includes a plurality of thin film transistors on the base substrate, which at least include a first transistor, a second transistor and a third transistor. Each of the plurality of thin film transistors includes an active layer. The active layer of at least one of the first transistor and the second transistor is located in the second semiconductor layer and contains an oxide semiconductor material. The active layer of the third transistor is located in the first semiconductor layer and contains a polysilicon semiconductor material. At least one of the first transistor and the second transistor has a dual-gate structure.