Abstract: A memory cell includes a flip-flop circuit that includes a first CMOS inverter circuit including a 1Ath transistor TR1 and a 1Bth transistor TR2 and a second inverter circuit including a 2Ath transistor TR3 and a 2Bth transistor TR4 and two transfer transistors TR5 and TR6. The 1Ath transistor TR1 and the 2Ath transistor TR2 are connected to a common first power supply line, and the 1Bth transistor TR3 and the 2Bth transistor TR4 are connected to a common second power supply line.

Abstract: The disclosure provides an array substrate, a display panel and a displaying device, relating to the technical field of display ambient light. The array substrate has an active area and a peripheral area located on at least one side of the active area. The array substrate comprises a brightness detection module and a reference module. The brightness detection module is arranged in the peripheral area, comprising at least one first thin-film transistor. The brightness detection module is configured to receive ambient light, generate an ambient light brightness detecting current signal in response to the ambient light and output the ambient light brightness detecting current signal. The reference module is arranged in the peripheral area, comprising at least one second thin-film transistor. The reference module is configured to, in a dark state without ambient light, generate and output a reference current signal.

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

Abstract: A method of manufacturing an electro-optically active device. The method comprising the steps of: etching a cavity on a silicon-on-insulator wafer; providing a sacrificial layer adjacent to a substrate of a lll-V semiconductor wafer; epitaxially growing an electro-optically active structure on the lll-V semiconductor wafer; etching the epitaxially grown optically active structure into an electro-optically active mesa; disposing the electro-optically active mesa in the cavity of the silicon-on-insulator wafer and bonding a surface of the electro-optically active mesa, which is distal to the sacrificial layer, to a bed of the cavity; and removing the sacrificial layer between the substrate of the lll-V semiconductor wafer and the electro-optically active mesa.

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

Abstract: A display device includes a first display region and a second display region having a lower pixel density than the first display region. A first pixel circuit in the first display region includes a first drive transistor, a first storage capacitor that stores a control voltage of the first drive transistor, and a first switch transistor that writes a data signal to the first storage capacitor. A second pixel circuit in the second display region includes a second drive transistor, a second storage capacitor that stores a control voltage of the second drive transistor, and a second switch transistor that writes a data signal to the second storage capacitor. A channel width of the second drive transistor is greater than a channel width of the first drive transistor. A channel width of the second switch transistor is greater than a channel width of the first switch transistor.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.

Abstract: A display device includes a substrate, a plurality of pixels provided to the substrate, a light emitting element and a plurality of transistors provided to each of the pixels, signal lines configured to supply a signal to the pixels, a first semiconductor layer and a second semiconductor layer provided in different layers in a direction perpendicular to the substrate and overlap at least partially in planar view, first gate electrodes each of which is provided in a region overlapping a part of the first semiconductor layer, a first insulating film provided between the first gate electrodes and the first semiconductor layer, and a second insulating film provided between the first semiconductor layer and the second semiconductor layer.

Abstract: Disclosed are a display substrate and a display device. The display substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines on the base substrate that intersect to surround a plurality of pixels; at least one thin film transistor on the base substrate and located in each pixel, each thin film transistor including a gate electrode, a first electrode and a second electrode; a storage capacitor on the base substrate and located in each pixel, the storage capacitor including a first capacitor electrode and a second capacitor electrode that are disposed oppositely and located in the same layer, wherein the first capacitor electrode comprises at least an electrode body; and a tip structure, the tip structure and the first capacitor electrode being located in the same layer, and the tip structure including a first tip sub-structure and a second tip sub-structure.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

Abstract: In order to minimize an additional non-output region that is generated when a wire bypasses a non-output region of a display, a mobile terminal is provided which comprises: a display panel including the non-output region; a TFT (Thin Film Transistor) substrate included in the display panel; a TFT wire that is provided on a front surface of the TFT substrate to form an output region and is isolated in the non-output region; a via hole formed at the isolated point of the TFT substrate; and a bypass wire for connecting the isolated TFT wire through the via hole.

Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

Abstract: Provided is a display device. The display device comprises a first substrate, wherein a first contact hole is defined in the first substrate, a barrier layer on the first substrate, wherein a second contact hole is defined in the barrier layer and connected to the first contact hole, a first connection line on the barrier layer and inserted into the second contact hole, a second substrate covering the first connection line and the barrier layer, and a thin-film transistor layer on the second substrate and including at least one thin-film transistor. The thin-film transistor layer further includes a second connection line connected between the first connection line and the at least one thin-film transistor.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening.

Abstract: A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.

Abstract: A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.

Abstract: The present disclosure relates to an insulation unit based on an array substrate and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display mechanism. The method for manufacturing the insulation unit based on the array substrate includes: providing an aluminum layer on a substrate; and anodizing the aluminum layer to oxidize the aluminum layer to form the insulation unit. The method for manufacturing the insulation unit based on the array substrate can manufacture an insulation unit with a better corrosion resistance.