Abstract: A method of fabricating suspended beam silicon carbide microelectromechanical (MEMS) structure with low capacitance and good thermal expansion match. A suspended material structure is attached to an anchor material structure that is direct wafer bonded to a substrate. The anchor material structure and the suspended material structure are formed from either a hexagonal single-crystal SiC material, and the anchor material structure is bonded to the substrate while the suspended material structure does not have to be attached to the substrate. The substrate may be a semi-insulating or insulating SiC substrate. The substrate may have an etched recess region on the substrate first surface to facilitate the formation of the movable suspended material structures. The substrate may have patterned electrical electrodes on the substrate first surface, within recesses etched into the substrate.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: A display panel includes first signal lines, second signal lines, first conductive patterns, second conductive patterns, at least one first switching unit and at least one second switching unit. An area of the first signal line is greater than that of the second signal line. Each first signal line is electrically connected to at least one first conductive pattern through at least one first switching unit. Each second signal line is electrically connected to at least one second conductive pattern through at least one second switching unit. The first switching unit includes at least one first thin film transistor, and the second switching unit includes at least one second thin film transistor. A channel width-to-length ratio of each first thin film transistor is greater than that of each second thin film transistor.

Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

Abstract: A method of manufacturing a display substrate, a display substrate and a display panel are provided. The method of manufacturing a display substrate includes: infiltrating an etching point of a film group with an etching solution, to form an infiltration groove at the etching point of a film group; and patterning a remaining part of the film group at the infiltration groove, to obtain a via hole penetrating the remaining part of the film group.

Abstract: A display panel and a method for manufacturing a display panel that includes a front side and a back side, the display panel including a substrate having a plurality of electrical components provided on a front side of the substrate and integrated circuits connected to the plurality of electrical components, the integrated circuits being embedded in the substrate. A plurality of edge contacts is also provided along edges of the substrate, where the plurality of edge contacts is electrically connected with the integrated circuits. An electrically conductive layer covers at least a part of the front side of the substrate and surrounds the plurality of electrical components, where the electrically conductive layer does not physically contact the embedded integrated circuits and provides electromagnetic interference (EMI) shielding to different components of the display panel.

Abstract: A display panel includes a plurality of sub-pixel structures and a plurality of transfer elements. The sub-pixel structures include a plurality of first sub-pixel structures. A data line of each of the first sub-pixel structures is disposed adjacent to a corresponding transfer element, and a scan line of each of the first sub-pixel structures is electrically connected to the corresponding transfer element. The first sub-pixel structures include a plurality of first-type sub-pixel structures and a plurality of second-type sub-pixel structures. When the display panel displays a grayscale picture, each of the first-type sub-pixel structures has first brightness, each of the second-type sub-pixel structures has second brightness. The first brightness is less than the second brightness. A total number of the first sub-pixel structures of the display panel is A, a number of the first-type sub-pixel structures in the first sub-pixel structures is a, and 50%<(a/A)<100%.

Abstract: The present disclosure illustrates a repair method for an active matrix substrate. The repair method includes steps: performing the broken-line inspection process to inspect whether the broken line exists on the first and second gate lines; if one first gate line is inspected to be broken, performing a source line repair-section forming process to cut off the cut portions of the second source lines disposed at two sides of a pixel electrode corresponding to a broken location of the first gate line, to form source line repair sections overlapping with the broken first gate line and the second gate line; performing a gate line repair-section forming process on the second gate line, adjacent to the broken first gate line, to cut off the cut portions of the second gate line to form a gate line repair section overlapping with the second source lines; and performing a connection process.

Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

Abstract: The present invention provides a display including: a substrate; a plurality of data lines disposed above the substrate; and a pixel electrode disposed above the plurality of data lines, and including: at least one first trunk and a plurality of second trunks extending along a first direction; a plurality of first branches; and a plurality of second branches, wherein distal ends of the plurality of first branches and distal ends of the plurality of second branches are staggered and connected to each other at positions corresponding to the plurality of data lines.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate.

Abstract: A pixel structure and a manufacturing method therefor, an array substrate, and a display device are provided. The pixel structure includes a pixel electrode, an active layer, a source/drain electrode layer, and a common electrode which are located on a base substrate. The pixel electrode is located between the base substrate and the common electrode. The source/drain electrode layer includes a first electrode and a second electrode which are electrically connected to the active layer, and the second electrode is electrically connected to the pixel electrode. The active layer is located between the base substrate and the source/drain electrode layer. The active layer includes a first surface close to the source/drain electrode layer. The source/drain electrode layer includes a second surface close to the active layer. Partial edge of the first surface is aligned with partial edge of the second surface.

Abstract: A pixel array substrate, including gate elements and transfer elements, is provided. The gate elements include an n-th gate element and an m-th gate element. The transfer elements include a n-th transfer element and an m-th transfer element electrically connected to the n-th gate element and the m-th gate element respectively. A peripheral portion of each of the transfer elements includes a first straight section. A peripheral portion of the n-th transfer element further includes a first lateral section. The first lateral section of the n-th transfer element and the first straight section of the n-th transfer element respectively belong to a first conductive layer and a second conductive layer. A peripheral portion of the m-th transfer element crosses over the first lateral section of the peripheral portion of the n-th transfer element.

Abstract: A display panel and a method for manufacturing the same, and a display device is provided. The display panel includes a display area including a plurality of gate lines arranged spaced apart in a first direction and a non-display area including a first and a second non-display area. At least one of the first or the second non-display area includes: a gate driving area including a plurality of gate driving units arranged spaced apart in the first direction and connected to the gate lines, a length of at least one gate driving unit being smaller than a length of a pixel in the first direction; a dummy gate driving area including a plurality of dummy gate driving units arranged spaced apart in the first direction; and a first trace area including a plurality of first traces connected to the dummy gate driving units and an external circuit.

Abstract: A display panel, a manufacturing method and a repair method thereof are provided. The display panel includes a flexible substrate and a plurality of bent traces. The flexible substrate includes a display portion, a bent portion, and a bezel portion being arranged in order. The bezel portion and the display portion are stacked through a bending in the bent portion. The bent portion is provided with the plurality of bent traces. Material of the bent traces includes a first material, and the first material is a conductive material having a melting point lower than 250° C. By adding the first material with the low melting point to the bent traces, when the bent traces are broken, the first material can be melted to flow by heating, thereby repairing the broken traces among the bent traces, whereby realizing the self-repair of the bent traces, increasing the process yield and reducing the production loss.

Abstract: Embodiments of the present disclosure provide a flexible array substrate, a manufacturing method thereof, and a flexible display device, which relate to the field of display technology, and can reduce the difficulty of wiring, decrease the IR drop, and improve the problem that the wiring is prone to breakage when bent. The flexible array substrate includes a substrate, the substrate including a first sub-substrate and a second sub-substrate which are stacked, the second sub-substrate including at least one via hole; a wiring layer disposed between the first sub-substrate and the second sub-substrate; and a pixel array layer disposed on a side of the second sub-substrate facing away from the first sub-substrate; the wiring layer including a wiring, wherein the pixel array layer is electrically connected to the wiring through the at least one via hole.

Abstract: This application discloses a method for manufacturing a display panel, a display panel, and a display device. The display panel has a display area and a peripheral area. The display panel includes a first substrate, a second substrate, a plurality of pixel elements, a plurality of data lines and scanning lines, and a plurality of color filters. The first substrate includes a first shading layer, the first shading layer being formed between two neighboring pixel elements to block the data lines or the scanning lines. The display area includes an opening area and a non-opening area, and the first shading layer is arranged only in the non-opening area. The second substrate includes a second shading layer arranged corresponding to the first shading layer. Each of the data lines and the scanning lines is blocked by at least one of the first shading layer and the second shading layer.

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.