Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film.

Abstract: A thin film transistor structure, a gate driver on array (GOA) circuit and a display device are provided. The thin film transistor structure defines a plurality of thin film transistors by patterning an active layer. Therefore, when a defect appears in the gate insulating layer of one of the plurality of thin film transistors and a leakage path is formed, other thin film transistors will not be affected. Therefore, a problem of functional failure of a whole thin film transistor structure can be avoided.

Abstract: A transparent electrode member includes a translucent base, and first transparent electrodes that are arranged side by side in a first direction on a first surface of the base. An insulating layer does not overlap partial regions PR when viewed in the direction of the normal to the first surface. A rectangular region in which a part other than the conductive portion is composed of the partial regions over the entire part is defined as a first rectangular region, a rectangular region in which at least the insulating layer is contained is defined as a second rectangular region, and a relationship between an area Sa of the part other than the conductive portion in the first rectangular region and an area Sb of a part other than the conductive portion in the second rectangular region satisfies Sa/Sb=1±0.3.

Abstract: Systems and methods are described for a display panel and a method of manufacturing the display panel. The systems and methods may provide for a substrate having a first surface and a second surface that face each other, a display unit including an organic light-emitting device arranged on the first surface of the substrate; and a thin-film encapsulation layer arranged on the display unit to shield the display unit, wherein an edge of the first surface or an edge of the second surface are inclined with respect to the first surface or the second surface. The inclined surfaces are designed to prevent damage to the display due to fine cracks during the manufacturing process as the display panel is trimmed or cut from a single base member. A display panel having improved strength characteristics may be manufactured, as well.

Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

Abstract: An Electro-Static Discharge (ESD) protection circuit including a Thin Film Transistor (TFT) arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.

Abstract: A field effect transistor includes a substrate; a semiconductor structure formed on a main face of the substrate, the semiconductor structure including a channel area; a first electrode and a second electrode between which extends the channel area, the first electrode including a plurality of portions spaced apart from each other, each portion of the first electrode contributing to forming an elementary transistor referred to as island; connection tracks for electrically connecting the portions of the first electrode to one another; and in which each portion of the first electrode is connected to a connection track through a fuse area, each fuse area associated with the portion of the first electrode of an island being capable of being broken in such a way as to electrically insulate said island if it is defective.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: An array substrate and a display device are disclosed.

Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.

Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

Abstract: A display includes a substrate, a first electrode base layer and a second electrode base layer spaced from each other on the substrate, a first electrode on the first electrode base layer and a second electrode on the second electrode base layer, a first inner bank between the first electrode base layer and the first electrode and a second inner bank between the second electrode base layer and the second electrode, and a light emitting element between the first electrode and the second electrode, at least one end portion of the light emitting element being electrically connected to the first electrode or the second electrode, wherein a side surface of one end portion of each of the first and second electrode base layers is at the same line as a side surface of an end portion of a corresponding one of the first and second electrodes.

Abstract: The present application discloses a manufacturing method for a display panel and the display panel, and the manufacturing method includes a manufacture procedure of forming an array substrate, where the manufacture procedure of forming an array substrate includes: forming a buffer layer with a preset pattern on a glass substrate; placing the glass substrate with the buffer layer formed thereon into an electrochemical deposition device, and performing electrochemical deposition to form a copper alloy metal layer corresponding to the buffer layer; heating and annealing the copper alloy metal layer to form a first metal layer; sequentially forming an insulating layer, an active layer, a second metal layer, a passivation layer and a transparent electrode layer on the first metal layer, where the first metal layer includes a buffer layer and a copper alloy metal layer.

Abstract: An electronic device is provided. The electronic device includes a substrate, a first wire, a first semiconductor element and a second semiconductor element. The substrate has a display region and a peripheral region adjacent to the display region. The first wire is disposed in the display region and the peripheral region. The first semiconductor element is disposed in the display region. The second semiconductor element is disposed in the peripheral region and adjacent to the first semiconductor element. The first semiconductor element and the second semiconductor element cross the first wire in two parts respectively and the two parts of the second semiconductor element is less than the two parts of the first semiconductor element in distance.

Abstract: An array substrate, a display panel, and a display device. The array substrate includes a substrate having a display region and a non-display region surrounding the display region. The display region includes a plurality of signal lines extending along a first direction. The non-display region includes at least three repair lead wires, and welding terminals connected to the repair lead wires in a one-to-one corresponding manner. The signal lines form overlapping regions together with an orthographic projection of at least one repair lead wire on the substrate.

Abstract: A display device is provided. A display device includes a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed to overlap the gate electrode; a source electrode disposed on the semiconductor pattern; a drain electrode disposed on the semiconductor pattern and facing the source electrode; and a pixel electrode connected to the drain electrode, wherein the drain electrode comprises a bar-shaped portion disposed on the semiconductor pattern and extending in one direction, a compensation portion connected to one distal end portion of the bar-shaped portion, a connecting portion connected to the other distal end portion of the bar-shaped portion, and an pad portion connected to the connecting portion and overlapping the pixel electrode, wherein the bar-shaped portion has a first width and at least portions of the compensation portion and the connecting portion have a second width that is greater than the first width.

Abstract: To provide a semiconductor film capable of realizing further enhancement of photoelectric conversion efficiency. The semiconductor film includes semiconductor nanoparticles and a compound represented by the following general formula (1), in which the compound represented by the general formula (1) is coordinated to the semiconductor nanoparticles. (In the general formula (1), X represents —SH, —COOH, —NH2, —PO(OH)2, or —SO2(OH), A1 represents —S, —COO, —PO(OH)O, or —SO2(O), and n is an integer of 1 to 3. B1 represents Li, Na, or K.

Abstract: A display device, including a thin film transistor, a transfer pad, and a pixel electrode, is provided. The thin film transistor includes a drain. The transfer pad is electrically connected to the drain. The pixel electrode is electrically connected to the transfer pad through a first opening of a first insulating layer. The first insulating layer is disposed between the transfer pad and the pixel electrode. A width of the first opening is greater than a width of the drain. The width of the first opening is smaller than a width of the transfer pad. The display device of the disclosure can improve the electron transfer between the pixel electrode and the drain.

Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.