Patents Examined by Peter Toby Brown
  • Patent number: 6124180
    Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: September 26, 2000
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Richard G. Taylor
  • Patent number: 6117746
    Abstract: A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: September 12, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won Jong Yoo
  • Patent number: 6096613
    Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: August 1, 2000
    Assignee: Acer Semiconductor Manufacturing Inc.
    Inventor: Shye-Lin Wu
  • Patent number: 6090686
    Abstract: The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 18, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: David C. Brady, Isik C. Kizilyalli, Pradip K. Roy, Hem M. Vaidya
  • Patent number: 6069051
    Abstract: A method of fabricating on chip metal-to-metal capacitors (MMCAP) uses planar processing with a flexible choice of dielectric, thickness and capacitor shape. The method provides a simpler process which has a better yield and more reliable structure by creating a metal-to-metal capacitor on a planar surface, not in deep trenches. In addition to the process simplicity, the method also allows the use of any dielectric materials which are needed by the product designer; e.g., higher or lower dielectric constant and also not limited by high etch rate difference. Because the inventive process is a planar process, there are no corners in the bottom of deep trenches to cause yield and reliability problems. The capacitor area can be adjusted to any shape because there are no edge effects.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: May 30, 2000
    Assignee: International Business Machines Corporation
    Inventors: Du B. Nguyen, Hazara S. Rathore, George S. Prokop, Richard A. Wachnik, Craig R. Gruszecki
  • Patent number: 6051460
    Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: April 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepak K. Nayak, Ming-Yin Hao
  • Patent number: 6048802
    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: April 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Avanzino, Darrell Erb, Robin Cheung, Rich Klein
  • Patent number: 6040613
    Abstract: Titanium aluminum nitrogen ("Ti--Al--N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti--Al--N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti--Al--N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti--Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: March 21, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Everett A. McTeer, Russell C. Zahorik, Scott G. Meikle
  • Patent number: 6030848
    Abstract: A manufacturing method for high quality GaN-based light emitting devices. The method enable effective growth of an Al.sub.y Ga.sub.1-y N (0.ltoreq.y.ltoreq.1) layer on an In.sub.x Ga.sub.1- N (0.ltoreq.x.ltoreq.1) layer by CVD. While holding or increasing the temperature after growing the InGaN layer at the temperature of T0 before growing the AlGaN at the temperature of T1 (T0.ltoreq.T1) in an atmosphere including a source of group V of elements, the present invention applies an inert gas as the carrier gas which includes a source of the group V elements. Therefore, the concentration of group V elements near the surface of the InGaN layer increases and the sublimation of the InGaN layer is prevented by increasing the steam pressure of the group V elements near the surface of the InGaN layer.
    Type: Grant
    Filed: April 16, 1997
    Date of Patent: February 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shozo Yuge, Hideto Sugawara
  • Patent number: 6010932
    Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: January 4, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Manny Kin F. Ma
  • Patent number: 6008536
    Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate and a heat spreader. The chip includes multiple I/O pads preferably arranged in a two-dimensional array on an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The substrate maintains its substantially planar shape during C4 heating. The heat spreader is thermally conductive and preferably dimensioned to substantially cover the upper surface of the substrate. An underside surface of the heat spreader includes a cavity dimensioned to receive the chip and multiple pins extending outwardly therefrom. The substrate includes multiple holes adapted to receive the pins of the heat spreader.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: December 28, 1999
    Assignee: LSI Logic Corporation
    Inventor: Atila Mertol
  • Patent number: 6004839
    Abstract: In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: December 21, 1999
    Assignee: NEC Corporation
    Inventors: Yoshihiro Hayashi, Nobuhiro Tanabe, Tsuneo Takeuchi, Shinobu Saito
  • Patent number: 6001676
    Abstract: Formed on a p-type semiconductor substrate are bipolar transistors and CMOS transistors. A bipolar transistor has a base extraction electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a polysilicon layer. A CMOS transistor has a gate electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a side-wall layer. The silicon nitride layer on the side-surface of the base extraction electrode is formed by the same fabrication step that the silicon nitride layer on the side-surface of the gate electrode is formed.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: December 14, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Shigeki Sawada, Takashi Furuta
  • Patent number: 5998861
    Abstract: An LSI chip has first electrodes. A chip carrier has a board, second electrodes arranged on a first surface of the board, third electrodes arranged on a second surface of the board, and wires connecting second electrodes to third electrode each other. Bumps combine the first electrodes of the LSI chip with the second electrodes of the chip carrier each other. Resin fills a space between a main surface of the LSI chip and a first surface of the board, so as to fix the bumps to each other. Ball electrodes are combined with third electrodes of the chip carrier.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichi Hiruta
  • Patent number: 5998814
    Abstract: A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a seco
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: December 7, 1999
    Assignee: Yamaha Corporation
    Inventors: Takahisa Yamaha, Seiji Hirade
  • Patent number: 5998859
    Abstract: A thin MCM packaging structure and technique is provided in which a thin film decal interconnect circuit is fabricated on a thin aluminum wafer. The thin-film decal interconnect employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die. A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities to hold one or more die to be mounted on the MCM structure. The die are oriented with their pads in contact with contact pads on the thin-film decal interconnect to which they are bonded and the cavities are filled with a liquid encapsulant and cured.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: December 7, 1999
    Assignee: MicroModule Systems, Inc.
    Inventors: Bradley L. Griswold, Chung Wen Ho, William C. Robinette, Jr.
  • Patent number: 5994211
    Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wei-Jen Hsia, Wilbur Catabay
  • Patent number: 5989963
    Abstract: A method of manufacturing a semiconductor device with a steep retrograde profile. The threshold voltage adjust dopant layer and the punchthrough prevent dopant layer are formed in the substrate. All surface capping layers are removed from the active device regions and, the semiconductor device is placed in a chamber and a high vacuum is established after which an inert atmosphere is introduced into the chamber. The anneal to repair the damage to the lattice and to activate the dopant ions in the dopant layers is done in the inert atmosphere with the surface of the substrate maintained clean, that is, free from a capping oxide or other layer formed on the surface of the substrate.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: November 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott D. Luning, David C. Greenlaw, Jonathan Fewkes
  • Patent number: 5990543
    Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: November 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Kevin Weaver, Terry Barrette
  • Patent number: RE36469
    Abstract: A logic module design is disclosed which incorporates an unencapsulated wafer section or sections. The disclosed module is an improvement over previous designs in that it is less expensive and easier to manufacture due to the reduced number of components and the complexity of the components, is faster and consumes less power because of its shorter trace lengths and smaller size, and is more reliable as a result of its greatly reduced number of interconnects.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: December 28, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett