Abstract: An improved method and composition for achieving a kinetically-controlled solder bond is disclosed having particular application to the fabrication of hybrid integrated circuits and optical subassemblies. The method involves the use of a solder layer, a quenching layer, and a control layer disposed between the solder layer and quenching layer, in which the control layer is advantageously comprised of a thin film of platinum. Additionally, a barrier layer, also preferably comprised of a thin film of platinum, is disposed between the solder layer and the parts to be bonded to prevent the oxidation of solder materials during the soldering process or later storage of the soldered parts.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel element to an amorphous silicon film 103. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Next, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A method of fabricating a semiconductor device includes the steps of, after sawing a semiconductor substrate into individual semiconductor chips in a state that the semiconductor substrate is covered by an adhesive tape, applying a dry gas to the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips, applying an infrared radiation to the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips, and curing the adhesive layer on the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips, by irradiating a ultraviolet radiation to the adhesive tape, wherein the step of applying the dry gas, the step of applying the infrared radiation and the said step of curing the adhesive layer are conducted substantially simultaneously.

Abstract: According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.

Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract: A power semiconductor module is specified in which a layer of foam is arranged under the housing cover in the housing. The foam not only enables mechanical support of the potting compound, so that the latter is prevented from becoming detached, but can also absorb a large pressure increase in the event of a short circuit by virtue of compression. In this way, a compensating volume is created without the housing being destroyed. The housing remains closed and no material is hurled into the surroundings.

Abstract: A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including; a semiconductor substrate; an epitaxial layer laminated on the semiconductor substrate; a buried collector of a first conductivity type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer; a base of a second conductivity type which is a lightly doped well and formed on the epitaxial layer; and an emitter of the first conductivity type and formed on the surface layer of the base of the second conductivity type; and in which the base is adapted to have impurity concentration and depth so that a punch-through is generated between the emitter and the collector of the electrostatic discharge protection dev

Abstract: A semiconductor device having a capacitor containing an insulator material having a high dielectric constant and high charge storing capability of the following formula: (A.sup.1).sub.x (A.sup.2).sub.2-x (D).sub.d (B.sup.1).sub.y (B.sup.2).sub.1-y O.sub.4 where A.sup.1 and A.sup.2 are cations, B.sup.1 and B.sup.2 are anions, 0.ltoreq.x.ltoreq.2 with the proviso that A.sup.1 and A.sup.2 are different types of atoms when 0<x<2, and 0.ltoreq.y.ltoreq.1 with the proviso that B.sup.1 and B.sup.2 are different types of atoms when 0<y<1, and D is an optional dopant in a total amount of 0.ltoreq.d.ltoreq.0.1.

Abstract: A dynamic random access memory (DRAM) and a method of manufacturing the same which is suitable for increasing the integration of a semiconductor device and suppressing the generation of a leakage current using a silicon-on-insulator (SOI) structure are disclosed. The semiconductor device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor layer pattern formed on the insulating film, a trench formed in the semiconductor substrate through the semiconductor layer pattern and the insulating film, an electrode of a capacitor formed in the trench for electrically connected to the semiconductor layer pattern, a gate insulating film formed on the semiconductor layer pattern, a gate electrode formed on the gate insulating film, and impurity regions formed in the semiconductor layer pattern.

Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate on a transferring substrate to which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.

Abstract: A multilayer polysilicon semiconductor device having a first layer of amorphous semiconductor deposited on the surface of an underlying substrate. The first layer is polycrystallized by applying an energy beam to the first layer. A second layer is deposited on the surface of the polycrystallized first layer, the second layer being made of amorphous semiconductor having the same composition as the first layer or polycrystalline semiconductor. Crystallinity of the second layer is changed by applying an energy beam to the second layer. The substrate may be heated when the energy beam is applied to the second layer.

Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56).

Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.

Abstract: The present invention relates to a method for manufacturing TFTs in which a gate electrode is first formed on a transparent glass substrate by depositing and patterning a first metal layer. Next, a first insulating layer, a semiconductor layer, impurity-containing semiconductor layer and a second insulating layer are deposited over the first metal layer and the substrate surface. The insulating layer is patterned followed by deposition of a second metal layer. First portions of the second metal layer and the impurity-containing semiconductor layer along with part of the second insulating layer are etched over the gate electrode (thereby forming source and drain electrodes) at the same time second portions of the second metal layer and impurity-containing semiconductor layer and portions of the semiconductor layer laterally spaced from the gate electrode are etched. As a result, the number of etching steps is reduced, and the second insulating layer controls the etching speed.

Abstract: A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a <100> orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.