Abstract: A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.

Abstract: An MRAM construction can include an MRAM device between a pair of substantially orthogonal conductive lines, with one of the substantially orthogonal conductive lines being configured to induce Hx within the device, and the other being configured to induce Hy within the device. A first pulse of current is passed along a first of the two conductive lines while passing at least two sequential pulses of current along a second of the two conductive lines. The sequential pulses include a pulse along a first direction of the second of the two conductive lines, and a pulse along a second direction opposite to the first direction.

Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: An output buffer has a data unit for buffering data for an off chip driver. The output buffer also includes an echo clock signal generator for generating an echo clock signal associated with the buffered data. The echo clock signal is generated responsive to either a buffer control signal that controls the data unit, or to the data itself. The buffer control signal or the data is mixed with an echo control signal to generate a reset signal. The echo control signal is outputted, responsive to the reset signal, as the echo clock signal. This prevents skew from developing between the data and the echo clock signal. A method includes buffering data for an off chip driver, and generating and outputting to the off chip driver an echo clock signal to accompany the data. The echo clock signal is generated responsive to either a buffer control signal that controls the data unit or to the data itself.

Abstract: A programmable non-volatile data storage calibration circuit stores a calibration code for a temperature sensor circuit of an IC, comprising a programmable array of addressable bi-state, bi-stable first circuit elements each comprising a fusible resistor. A power supply controlled by a data input signal addresses the first circuit elements to be switched from a first to a second state in the fusible resistor state, the supply, and a clock signal applied to an I/O terminal clocks the data input signal to the interpreter circuit. The interpreter circuit sequentially selects and addresses the first circuit elements and enables switching of the first circuit elements when the supply voltage is at its maximum, blowing a selected fusible resistor. A second, similar circuit element is switched to its second state after programming the calibration circuit to prevent its further programming.

Abstract: An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided in each memory cell. One sample of an analog signal is stored in one memory device, and one sample of that signal that is out of phase is stored in the other memory device.

Abstract: The present invention relates to a memory circuit (MEM) able to receive a first data block comprising a number of components and coming from an external memory (EXT) for them to be written (W) in an internal memory. The memory circuit is also able to supply (R) to an output device (FIL) a second data block comprising a component of said data. The memory circuit comprises data banks able to receive data words, and address controllers associated to the data banks and able to organize a reading or writing access of the data in the internal memory of the memory circuit, while minimizing the number of data banks used. Thus it is possible to rapidly read or write in the memory circuit at relatively low cost.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.

Abstract: A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control at least some of the logic portions of each CAM circuit. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.

Abstract: Devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. An oscillator generates an oscillating signal, and a charge pump generates a pumping voltage at a pumping node responsive to the oscillating signal. A first switching circuit is coupled to the pumping node, and outputs from the pumping voltage a first voltage to the first component. A second switching circuit is coupled to the pumping node, and outputs from the pumping voltage a second voltage to the second component. The first and second output voltages may optionally be sensed. The oscillator may be triggered and the first and second switching circuits may be controlled as needed to maintain the sensed first and second voltages at desired values and/or ranges.

Abstract: A resistance variable device and a method for using the same. The device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on the body. The body includes a surface extending from one of the electrodes to the other of the electrodes. The surface has at least one surface striation extending from proximate the one electrode to proximate the other electrode at least when the body of said material is in a highest of selected resistance setable states. The method includes applying a first voltage between the one and the other electrodes to establish a negative and a positive electrode effective to form a conductive path formed of at least some material derived from the voltage or current controlled resistance setable material and on the surface along at least a portion of the at least one striation.

Abstract: A method for liquid phase deposition, including the steps of providing at least two raw materials from at least two supply devices of a saturation reaction system into a mixture trough and stirring until saturation occurs, filtering out unnecessary solid-state particles, and providing saturated and filtered liquid into an over-saturation reaction trough of a steady-flow over-saturation loop reaction system and stopping the saturated and filtered liquid when the over-saturation reaction trough is filled and the saturated and filtered liquid over-flows into a liquid level control trough to a pre-determined level. The method also includes the steps of providing a substrate in the over-saturation reaction trough, providing reactants from at least two supply devices into the over-saturation reaction trough, and depositing a thin film onto the substrate when the saturated liquid becomes over-saturated.

Abstract: An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.

Abstract: A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.

Abstract: A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). Th method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) with a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) with a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: A gas is supplied at a certain partial pressure for a chemical reaction with a top surface of a base in a transistor. The top surface of the base is heated to a certain temperature to promote the chemical reaction. For example, the gas can be oxygen, the base can be an epitaxial single crystal silicon-germanium base of a heterojunction bipolar transistor (“HBT”), and the chemical reaction can be oxidation of the silicon in the top surface of the silicon-germanium base. The partial pressure of oxygen is maintained at 0.1 atmosphere and the top surface of the base is heated using rapid thermal processing (“RTP”) to a temperature of 500° C. The chemical reaction forms a dielectric layer on the top surface of the base. For example, using oxygen as stated above, a dielectric layer of silicon oxide (“interfacial oxide”) is formed. Controlling the thickness and density of the interfacial oxide causes the gain of the transistor to be as desired.

Abstract: In the thin film resonator, a piezoelectric membrane is disposed over a substrate. A first support structure defines a space over the substrate and supports the edges of the piezoelectric membrane such that the piezoelectric membrane is disposed over this space. A further support structure is disposed within the space to the piezoelectric membrane.

Abstract: A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C.