Abstract: A method of making a connection component for a microelectronic element includes providing a sheet comprising an electrically conductive layer, a photoresist layer overlying the conductive layer and a photoimageable dielectric layer disposed under the conductive layer. The method includes lithographically forming at least one opening in the photoresist layer to uncover a portion of the conductive layer, forming a plurality of circuit features from the conductive layer by removing the uncovered portion of the conductive layer, at least some of the circuit features being leads, and lithographically forming at least one aperture in the photoimageable dielectric layer.

Abstract: A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

Abstract: A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.

Abstract: The present invention provides apparatus, systems, and methods related to the manufacture of integrated circuits. Specifically, embodiments of the present invention include apparatus designed to provide thorough and reliable fluid mixture for gases used in a semiconductor processing system. In one embodiment of the invention, the gas mixing apparatus comprises a gas mixer housing having a gas inlet, a fluid flow channel, and a gas outlet. The fluid flow channel is fluidly coupled to a plurality of gas sources. The majority of the gas mixture occurs in the fluid flow channel which comprises one or more fluid separators for separating the gas into two or more gas portions and one or more fluid collectors for allowing the gas portions to collide with each other to mix the gas portions. This separation and collection of the gas portions results in a thoroughly mixed gas.

Abstract: There is disclosed a method of manufacturing a CMOS transistor, by which ion implantation process is selectively performed to the gate formed region of a polysilicon film after a NMOS transistor region and a PMOS transistor region are defined in the process of manufacturing a CMOS transistor. Thus, it can obtain a reliable device by solving the problem occurring when polysilicon films doped with different impurities are simultaneously etched and the problem that a tungsten film is oxidized due to a selective oxidization process after forming a tungsten gate electrode.

Abstract: A process for fabricating a MOSFET device, featuring a narrow lateral delta doping, or a narrow anti-punchthrough region, located in the center of the MOSFET channel region, has been developed. The process features formation of the narrow, anti-punchthrough region, via use of an ion implantation procedure, performed using an opening, comprised with sidewall spacers, as an implant mask. After formation of the narrow, anti-punchthrough region, the sidewall spacers are removed, and a gate insulator layer, and a polysilicon gate structure, are formed in the spacerless opening, defining a channel region wider than the narrow, anti-punchthrough region.

Abstract: A semiconductor integrated circuit according to the present invention comprises a synchronous SRAM, a signal generation circuit generating a chip selection signal, a clock signal etc. supplied to the synchronous SRAM, a voltage set circuit setting the voltage of a system power supply line and a controller controlling the signal generation circuit and the voltage set circuit. When setting the synchronous SRAM in a power down mode, the chip selection signal is set in a nonselective state and the power supply voltage of the system power supply line is stepped down to a standby potential. Thus, the synchronous SRAM enters a standby state having extremely low power consumption.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: Semiconductor wafers are glued onto a carrier foil which is stretched across a frame. Instead of restretching the carrier foil directly at a processing machine, the foil is restretched on an adapter frame which can be stored and then later manipulated in the processing machine. The adapter frame includes a clamping ring, a base ring, and a threaded ring which secures the carrier foil.

Abstract: A crack-preventive substrate for fabricating a solder mask in a device site region includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. As a result, the crack lines generated on the solder mask layer at the perimeter of the substrate will not develop toward the solder mask in the device site region.

Abstract: A loading area capable of forming a sealed space in co-operation with a reaction chamber is provided. In a state in which the inner space of the reaction chamber is separated from the inner space of the loading area by a shutter plate, the oxygen concentrations in the reaction chamber and the loading area are both adjusted to a specific concentration. After both the oxygen concentrations coincide with each other at the specific value, semiconductor wafers held on a wafer boat are inserted from the loading area into the reaction chamber by a boat lifter.

Abstract: A process for forming a groove in a semiconductor substrate, to be used to fabricate grooved gate, MOSFET devices, has been developed. The process features the use of an insulator mask, used as an etch mask for definition of the groove feature in the semiconductor substrate. A selective, anisotropic RIE procedure, using an etchant with a specific etch rate ratio of silicon, (semiconductor substrate), to silicon oxide, (insulator mask), is used to establish the desired groove depth, in the semiconductor substrate. The combination of a specific thickness of insulator shape, and a specific etch rate ratio for the selective, anisotropic RIE procedure, allows the desired depth of the groove to be established when the insulator shape is completely removed from the top surface of the semiconductor substrate.

Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of identical bare chips 1 for memory are COB-mounted on a substrate 2, and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Four-chip, two-chip, and one-chip memory modules 10 are produced by cutting the substrate 2 and combining bare chips 1 which are judged to be nondefective chips.

Abstract: A method for making contact with a covered semiconductor layer through a contact hole, includes producing a contact hole in an insulator layer for making contact with at least one covered semiconductor layer. A heavily doped polysilicon layer is produced on the surface of the insulator layer and the contact hole is at least partially filled with heavily doped polysilicon. A metal layer is applied on the heavily doped polysilicon layer for establishing an ohmic connection to the outside. A semiconductor component fabricated according to the method is also provided.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

Abstract: Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film into a desired shape with a first sidewall and a second and opposite sidewall. A passivating oxide film is formed with a preselected thickness on the first and second sidewalls by oxidizing the silicon structure with a heated aqueous solution of ammonium hydroxide and hydrogen peroxide. Gate electrode formation with an oxide coating film of known thickness is provided. Linewidth metrology accuracy may be improved.

Abstract: A method of making a capacitor on a conductive surface, preferably on a polysilicon surface includes contamination cleaning the surface with a high density plasma (HDP) of a first gaseous agent, such as hydrogen, then growing a silicon nitride barrier layer on the surface using a high density plasma (HDP) of nitrogen. A layer of tantalum oxide is then deposited on the silicon nitride layer to form a capacitor dielectric layer. A second silicon nitride layer is then grown on the capacitor dielectric layer, also using an HDP nitrogen plasma with the addition of a silicon containing gas, such as silane. Finally, a conductive layer is deposited on the second silicon nitride layer to form the capacitor. The HDP plasma is heated using an inductively coupled radio frequency generator. The invention also includes a capacitor constructed on a conductive surface by the method of the invention.

Abstract: The memory cells at the very edge of an array are susceptible variations in transistor channel length and other attributes due to lithographic proximity effects. To reduce these undesirable edge effects, it is common to add non-functional sacrificial rows and columns of nearly identical memory cells around the periphery of a memory array. These “guard” cells (i.e., “end” cells, or “edge” cells) may provide, for at least the lower masking layers, a homogeneous lithographic environment at the edge of the functional array, but unfortunately consume area without adding to the storage capacity of the array. To save area, a group of functional memory cells in one array may also be used as guard cells for another memory array. The memory cells of the one array may, for example, be redundant memory cells serving the other memory array.

Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.