Abstract: An improved integrated circuit device that has an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then, a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfissure propagation is substantially prevented by (a) forming a compressive hard mask on a surface of a non-compressive material layer that is to be patterned by lithography and etching; (b) forming a patterned photoresist on said hard mask, wherein a portion of said hard mask is exposed; (c) removing said exposed portion of said hard mask so as to expose a portion of said non-compressive material layer; and (d) transferring said pattern from said patterned photoresist to said exposed portion of said material layer by etching, wherein said hard mask is selective to said etching and thus substantially prevents the propagation of photoresist microfissures to said material layer.

Abstract: The present invention discloses a method of forming an isolation region in a silicon-containing substrate. The method includes forming a mask layer on the silicon-containing substrate. A window is subsequently formed in the mask layer to expose the isolation area to be formed in the substrate. An oxygen-containing region is formed in the substrate by introducing oxygen-containing ions through the window in the mask layer. Then, the oxygen-containing region is subjected to a thermal treatment, thereby resulting in a silicon oxide insulator (SiOx) for isolating electronic devices.

Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: In a parallel-plate type plasma processing apparatus including an upper electrode having a plurality of gas introducing inlets and a support table serving as a lower electrode opposed to the upper electrode and having a silicon wafer thereon, the open ends of the inlets are expanded in their diameter directions.

Abstract: A method of fabricating an SrRuO3 thin film is disclosed. The method utilizes a multi-step deposition process for the separate control of the Ru reagent, relative to the Sr reagent, which requires a much lower deposition temperature than the Sr reagent. A Ru reagent gas is supplied by a bubbler and deposited onto a substrate. Following the deposition of the Ru reagent, the Sr liquid reagent is vaporized and deposited onto the Ru layer.

Abstract: An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

Abstract: A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.

Abstract: A method for forming silicide on a semiconductor wafer. The semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a metal layer positioned on the doped silicon layer, and a barrier layer covering the metal layer. A first rapid thermal processing (RTP) step is performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide. The barrier layer and the portions of the metal layer that have not reacted with silicon are then removed. A dielectric layer is formed on the transitional silicide. Finally, a second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the silicide.

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells.

Abstract: A process for the anisotropic etching of a dielectric organic polymer material using a plasma is provided. The gas phase of the plasma may include a gas mixture of O2/NH3, O2/H2O, O2/CH4 or O2/H2. The oxygen concentration of the gas mixture may be less than 40% by volume. The process may include the fabrication of metal interconnects in a damascene-type structure of an integrated circuit.

Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.

Abstract: The present invention provides methods for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density. A gate layout defining gate areas on the gate layer is provided along with a diffusion layout defining active diffusion areas over a semiconductor substrate. For the gate layout, a pattern density is determined. Then, the areas not occupied by the gate areas and the diffusion areas are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns with each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities. Among the set of predefined fill patterns, a predefined fill pattern is selected for producing the target pattern density. Then, the gate layer is filled by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions.

Abstract: A method of making a light emitting diode (LED) is disclosed. An emitting light absorbed by a substrate can be prevented by using a metal with high conductivity and high reflectivity and a bonding process can be produced at a lower temperature and a better welding performance can be obtained by using a solder layer could be fused into a liquid-state. Furthermore, an industry standard vertical LED chip structure is provided and only requiring a single wire bond that results in easy LED assembly and the manufacture cost can be reduced. An LED chip size can be greatly reduced and with good heat dissipation, therefore the LED has better reliability performance and can be operated at much higher current.

Abstract: A method for making a semiconductor device is provided. In the method, an insulating layer is formed over a semiconductor substrate, and a groove is formed in the insulating layer. Then, a first conductive layer, a first mask layer, a second conductive layer, and a second mask layer are sequentially and conformably formed on an upper surface of the insulating layer and an inner surface of the groove to form a laminated layer. Afterwards, the laminated layer is anisotropically etched to form a multiple cylindrical structure in the groove, and a multiple cylindrical electrode is formed based on the multiple cylindrical structure. Subsequently, a dielectric layer and a plate electrode are sequentially formed on the multiple cylindrical electrode to create a capacitor.

Abstract: A method for producing reliable contacts in microelectronic devices and contacts produced thereby are provided. In one embodiment of the invention, a first conductive layer is formed over a first dielectric layer. The first conductive layer contains a pattern etched therein. A second dielectric layer is deposited over the first conductive layer and a via is etched therein over the pattern, thus exposing a portion of the pattern and the first conductive layer. The structure is then further etched to remove a portion of the first dielectric layer using the exposed portions of the first conductive layer as a mask. The structure is then subject to an isotropic etch to create undercuts in the first dielectric layer underneath the exposed portions of the first conductive layer. A conductive material can then be deposited into the via to fill the undercut, thus contacting the first conductive material on the exposed top, sides, and underside of the layer to produce a highly reliable contact.

Abstract: The present invention relates to a method of crystallizing an amorphous silicon layer which is carried out by depositing a crystallization-inducing substance on an amorphous silicon layer on crystallizing the amorphous silicon layer by metal-induced crystallization whereby speed of crystallizing silicon is increased and metal contamination by MIC is reduced. The present invention includes the steps of depositing a crystallizing-induced layer of an induced substance for crystallizing silicon on an amorphous silicon layer wherein the crystallizing induced layer is formed to the thickness under 0.03 angstroms, and treating thermally the amorphous silicon layer on which the crystallizing-induced layer is deposited.

Abstract: This invention discloses a method of manufacturing a semiconductor device which comprises the steps of: forming gate electrodes on a semiconductor substrate having a cell region and a peripheral region; forming spacers at both side walls of the gate electrodes; implanting impurity into the semiconductor substrate of the peripheral region; forming a growth suppression layer on gate electrodes and surface of the semiconductor substrate in the peripheral region; forming doped epitaxial layers over predetermined portions of the semiconductor substrate in the cell region so that the impurity implanted into the semiconductor substrate in the peripheral region is diffused in the semiconductor substrate to form junction regions and impurity existing in the doped epitaxial layers of the cell region is diffused into the semiconductor substrate; and removing the growth suppression layer.